AD9627 datasheet(19/77 Pages) AD

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AD9627

Rev. B | Page 18 of 76

PIN 1

INDICATOR

DRVDD

DNC

D0– (LSB)

D0+ (LSB)

D1–

D1+

D2–

D2+

DCO–

DCO+

D3–

D3+

D4–

D4+

D5–

SCLK/DFS

SDIO/DCS

AVDD

VIN+B

VIN–B

RBIAS

CML

SENSE

VREF

VIN–A

VIN+A

AVDD

SMI SDFS

SMI SCLK/PDWN

SMI SDO/OEB

AD9627

PARALLEL LVDS

TOP VIEW

(Not to Scale)

EXPOSED PADDLE, PIN 0

(BOTTOM OF PACKAGE)

NOTES

1. DNC = DO NOT CONNECT.

2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.

Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)

Table 12. Pin Function Descriptions (Interleaved Parallel LVDS Mode)

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

20, 64

DRGND

Ground

Digital Output Ground.

1, 21

DRVDD

Supply

Digital Output Driver Supply (1.8 V to 3.3 V).

24, 57

DVDD

Supply

Digital Power Supply (1.8 V Nominal).

36, 45, 46

AVDD

Supply

Analog Power Supply (1.8 V Nominal).

AGND

Ground

Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.

2, 3, 62,

DNC

Do Not Connect.

ADC Analog

VIN+A

Input

Differential Analog Input Pin (+) for Channel A.

VIN−A

Input

Differential Analog Input Pin (−) for Channel A.

VIN+B

Input

Differential Analog Input Pin (+) for Channel B.

VIN−B

Input

Differential Analog Input Pin (−) for Channel B.

VREF

Input/Output

Voltage Reference Input/Output.

SENSE

Input

Voltage Reference Mode Select. See Table 14 for details.

RBIAS

Input/Output

External Reference Bias Resistor.

CML

Output

Common-Mode Level Bias Output for Analog Inputs.

CLK+

Input

ADC Clock Input—True.

CLK−

Input

ADC Clock Input—Complement.

ADC Fast Detect Outputs

FD0+

Output

Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 17 for details.

FD0−

Output

Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 17 for details.

FD1+

Output

Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 17 for details.

FD1−

Output

Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 17 for details.

FD2+

Output

Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 17 for details.

FD2−

Output

Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 17 for details.

FD3+

Output

Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 17 for details.

FD3−

Output

Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 17 for details.

Digital Input

SYNC

Input

Digital Synchronization Pin. Slave mode only.

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