LAN9220 datasheet(6/142 Pages) MICROCHIP

6 / 142 page

LAN9220

DS00002417A-page 6

 2006-2017 Microchip Technology Inc.

1.2

Internal Block Overview

This section provides an overview of each of these functional blocks as shown in Figure 1-2, "Internal Block Diagram".

FIGURE 1-2:

INTERNAL BLOCK DIAGRAM

1.3

10/100 Ethernet PHY

The LAN9220 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY can be configured

for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation in either full or half duplex configura-

tions. The PHY block supports HP Auto-MDIX and auto-negotiation.

Minimal external components are required for the utilization of the Integrated PHY.

1.4

10/100 Ethernet MAC

The transmit and receive data paths are separate within the MAC allowing the highest performance especially in full

duplex mode. The data paths connect to the PIO interface Function via separate busses to increase performance. Pay-

load data as well as transmit and receive status is passed on these busses.

A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is accessible from the

host through the PIO interface function.

On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent Interface) port

internal to the LAN9220. The MAC CSR's also provide a mechanism for accessing the PHY’s internal registers through

the internal SMI (Serial Management Interface) bus.

The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive FIFO which is sep-

arate from the TX and RX FIFOs. The FIFOs within the MAC are not directly accessible from the host interface. The

differentiation between the TX/RX FIFO memory buffers and the MAC buffers is that when the transmit or receive pack-

ets are in the MAC buffers, the host no longer can control or access the TX or RX data. The MAC buffers (both TX and

RX) are in effect the working buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first

to the RX FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode and

will queue an entire frame before beginning transmission.

10/100

Ethernet

PHY

10/100

Ethernet

MAC

2kB to 14kB

Configurable TX FIFO

2kB to 14kB

Configurable RX FIFO

Interrupt

Controller

GP Timer

PIO

Controller

3.3V to 1.8V

Core Regulator

PLL

25MHz

+3.3V

EEPROM

Controller

EEPROM

(Optional )

RX Status FIFO

TX Status FIFO

MIL - TX Elastic

Buffer - 2K bytes

MIL - RX Elastic

Buffer - 128 bytes

Power

Management

IRQ

FIFO _SEL

PME

Wakup Indicator

Host Bus Interface

(HBI)

16-bit SRAM I/F

RX Checksum

Offload Engine

TX Checksum

Offload Engine

LAN

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