LAN9220 datasheet(88/142 Pages) MICROCHIP

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LAN9220

DS00002417A-page 88

 2006-2017 Microchip Technology Inc.

Flow Control on Any Frame (FCANY). When this bit is set, the LAN9220

will assert back pressure, or transmit a pause frame when the AFC level is

reached and any frame is received. Setting this bit enables full-duplex flow

control when the LAN9220 is operating in full-duplex mode.

When this mode is enabled during half-duplex operation, the Flow Controller

does not decode the MAC address and will send a pause frame upon

receipt of a valid preamble (i.e., immediately at the beginning of the next

frame after the RX data FIFO level is reached).

When this mode is enabled during full-duplex operation, the Flow Controller

will immediately instruct the MAC to send a pause frame when the RX data

FIFO level is reached. The MAC will queue the pause frame transmission

for the next available window.

Setting this bit overrides bits [3:1] of this register.

R/W

TABLE 5-5:

BACKPRESSURE DURATION BIT MAPPING

Backpressure Duration

[19:16]

100Mbs Mode

10Mbs Mode

5uS

7.2uS

10uS

12.2uS

15uS

17.2uS

25uS

27.2uS

50uS

52.2uS

100uS

102.2uS

150uS

152.2uS

200uS

202.2uS

250uS

252.2uS

300uS

302.2uS

350uS

352.2uS

400uS

402.2uS

450uS

452.2uS

500uS

502.2uS

550uS

552.2uS

600uS

602.2uS

Bits

Description

Type

Default

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