S71PL254 datasheet(106/196 Pages) SPANSION

106 / 196 page

106

Type 2 pSRAM

pSRAM_Type02_15A0 May 3, 2004

Advance

I n f o rmation

1. 16Mb: A2 ~ A19, 32Mb: A2 ~ A20, 64Mb: A2 ~ A21.

tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to

output voltage levels.

At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device

to device interconnection.

tOE(max) is met only when OE# becomes enabled after tAA(max).

If invalid address signals shorter than min. tRC are continuously repeated for over 4µs, the device needs a normal read

timing (tRC) or needs to sustain standby state for min. tRC at least once in every 4µs.

Write Timings

Figure 29. Write Cycle #1 (WE# Controlled)

Figure 30. Write Cycle #2 (CS1# Controlled)

Address

CS1#

Data Undefined

UB#, LB#

WE#

Data in

Data out

tWC

tCW

tWR

tAW

tBW

tWP

tAS

tDH

tDW

tWHZ

tOW

High-Z

Data Valid

CS2

Address

Data Valid

UB#, LB#

WE#

Data in

Data out

High-Z

tWC

tCW

tAW

tBW

tWP

tDH

tDW

tWR

tAS

CS1#

CS2

S71PL254 Datasheet(PDF) 106 Page - SPANSION

S71PL254 Datasheet(HTML) 106 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL