S71PL254 datasheet(108/196 Pages) SPANSION

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108

pSRAM Type 3

pSRAM_Type03_06A0 February 25, 2004

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I n f o rmation

pSRAM Type 3

16 Megabit (1M x 16) CMOS Pseudo SRAM

Features

Organized as 1M words by 16 bits

Fast Cycle Time: 70 ns

Standby Current: 100 µA

Deep power-down Current: 10 µA (Memory cell data invalid)

Byte data control: LB# (DQ0 - 7), UB# (DQ8 - 15)

Compatible with low-power SRAM

Single Power Supply Voltage: 3.0V±0.3V

Description

pSRAM Type 3 currently includes only a 16M bit device, organized as 1M words

by 16 bits. It is designed with advanced CMOS technology specified RAM featur-

ing low-power static RAM-compatible function and pin configuration. This device

operates from a single power supply. Advanced circuit technology provides both

high speed and low power. It is automatically placed in low-power mode when

CS1# or both UB# and LB# are asserted high or CS2 is asserted low. There are

three control inputs. CS1# and CS2 are used to select the device, and output en-

able (OE#) provides fast memory access. Data byte control pins (LB#,UB#)

provide lower and upper byte access. This device is well suited to various micro-

processor system applications where high speed, low power and battery backup

are required.

Pin Description

A0 – A19

Address Inputs

DQ0 – DQ15

Data Inputs/Outputs

CE1#

Chip Enable

CE2

Deep Power Down

OE#

Output Enable

WE#

Write Control

LB#

Lower Byte Control

UB#

Upper Byte Control

VCC

Power Supply

VSS

Ground

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