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S71PL254 Datasheet(PDF) 111 Page - SPANSION |
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S71PL254 Datasheet(HTML) 111 Page - SPANSION |
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111 / 196 page ![]() February 25, 2004 pSRAM_Type03_06A0 pSRAM Type 3 111 Advance I n f o rmatio n tWC Write Cycle Time 70 - ns tWP Write Pulse Width 50 - ns tAW Address Valid to End of Write 60 - ns tCW Chip Enable to End of Write 60 - ns tBW Data Byte Control to End of Write 60 - ns tAS Address Set-up Time 0 - ns tWR Write Recovery Time 0 - ns tWZH WE# Low to Output High-Z - 20 ns tOW WE# High to Output in High-Z 5 - ns tDW Data to Write Overlap 35 - ns tDH Data Hold Time 0 - ns tWEH WE# High Time 5 10 ns Table 33. AC Test Conditions Parameter Condition Output load 50 pF + 1 TTL Gate Input pulse level 0.4 V, 2.4 Timing measurements 0.5 × VCC tR, tF 5 ns Note: Including scope and jig capacitance Figure 33. AC Test Loads Table 32. AC Characteristics and Operating Conditions (TA = -25°C to 85°C, VDD = 2.6 to 3.3V) (Continued) Cycle Symbol Parameter 70 Unit Min Max CL RL = 50 Ω Z0= 50 Ω DOUT VL = 1.5 V = 50 pF (see Note) |
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