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S71PL254 Datasheet(PDF) 115 Page - SPANSION |
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S71PL254 Datasheet(HTML) 115 Page - SPANSION |
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115 / 196 page ![]() February 25, 2004 pSRAM_Type03_06A0 pSRAM Type 3 115 Advance I n f o rmatio n Figure 40. Deep Power-down Mode Figure 41. Power-up Mode Note: The S71JL064HA0 Model 61 has a timing that is not supported at read operation. Data will be lost if your system has multiple invalid address signal shorter than tRC during over 15µs at the read operation shown above. Figure 42. Abnormal Timing Normal Operation Normal Operation 1 µs Suspend Wake Up Deep Power Down Mode 200 µs CE2 Mode CE1# 200 s VCC CE2 CE1# µ < tRC CE1# WE# Address > 15µs |
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