S71PL254 datasheet(119/196 Pages) SPANSION

119 / 196 page

August 30, 2004 pSRAM_Type04_18A0

pSRAM Type 4

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I n f o rmatio n

Table 36. Switching Characteristics

Notes:

1. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of VCC(typ.) /2, input pulse levels of

0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance.

2. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state.

3. High-Z and Low-Z parameters are characterized and are not 100% tested.

4. To achieve 55-ns performance, the read access should be CE# controlled. In this case tACE is the critical parameter and tSK is

satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable

within 10 ns after the start of the read cycle.

5. The internal write time of the memory is defined by the overlap of WE#, CE#1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All

signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input set-

up and hold timing should be referenced to the edge of the signal that terminates write.

Parameter

Description

Min

Max

Unit

Read Cycle

tRC

Read Cycle Time

tAA

Address to Data Valid

tOHA

Data Hold from Address Change

tACE

CE#1 Low and CE2 High to Data Valid

tDOE

OE# Low to Data Valid

tLZOE

OE# Low to Low Z (note 2, 3)

tHZOE

OE# High to High Z (note 2, 3)

tLZCE

CE#1 Low and CE2 High to Low Z (note 2, 3)

tHZCE

CE#1 High and CE2 Low to High Z (note 2, 3)

tDBE

BHE# / BLE# Low to Data Valid

tLZBE

BHE# / BLE# Low to Low Z (note 2, 3)

tHZBE

BHE# / BLE# High to High Z (note 2, 3)

tSK (note 4)

Address Skew

Write Cycle (note 5)

tWC

Write Cycle Time

tSCE

CE#1 Low an CE2 High to Write End

tAW

Address Set-Up to Write End

tHA

Address Hold from Write End

tSA

Address Set-Up to Write Start

tPWE

WE# Pulse Width

tBW

BLE# / BHE# LOW to Write End

tSD

Data Set-up to Write End

tHD

Data Hold from Write End

tHZWE

WE# Low to High Z (note 2, 3)

tLZWE

WE# High to Low Z (note 2, 3)

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