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CS5530A Datasheet(PDF) 150 Page - National Semiconductor (TI) |
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CS5530A Datasheet(HTML) 150 Page - National Semiconductor (TI) |
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150 / 259 page  www.national.com 150 Revision 1.1 Register Descriptions (Continued) Table 4-13. ISA Legacy I/O Registers Summary I/O Port Type Name Reference DMA Channel Control Registers (Table 4-27) 000h R/W DMA Channel 0 Address Register Page 220 001h R/W DMA Channel 0 Transfer Count Register Page 220 002h R/W DMA Channel 1 Address Register Page 220 003h R/W DMA Channel 1 Transfer Count Register Page 220 004h R/W DMA Channel 2 Address Register Page 220 005h R/W DMA Channel 2 Transfer Count Register Page 220 006h R/W DMA Channel 3 Address Register Page 220 007h R/W DMA Channel 3 Transfer Count Register Page 220 008h Read DMA Status Register, Channels 3:0 Page 220 Write DMA Command Register, Channels 3:0 Page 220 009h WO Software DMA Request Register, Channels 3:0 Page 221 00Ah R/W DMA Channel Mask Register, Channels 3:0 Page 221 00Bh WO DMA Channel Mode Register, Channels 3:0 Page 221 00Ch WO DMA Clear Byte Pointer Command, Channels 3:0 Page 221 00Dh WO DMA Master Clear Command, Channels 3:0 Page 221 00Eh WO DMA Clear Mask Register Command, Channels 3:0 Page 221 00Fh WO DMA Write Mask Register Command, Channels 3:0 Page 221 0C0h R/W DMA Channel 4 Address Register (Not used) Page 221 0C2h R/W DMA Channel 4 Transfer Count Register (Not Used) Page 221 0C4h R/W DMA Channel 5 Address Register Page 221 0C6h R/W DMA Channel 5 Transfer Count Register Page 221 0C8h R/W DMA Channel 6 Address Register Page 221 0CAh R/W DMA Channel 6 Transfer Count Register Page 221 0CCh R/W DMA Channel 7 Address Register Page 221 0CEh R/W DMA Channel 7 Transfer Count Register Page 222 0D0h Read DMA Status Register, Channels 7:4 Page 222 Write DMA Command Register, Channels 7:4 Page 222 0D2h WO Software DMA Request Register, Channels 7:4 Page 222 0D4h R/W DMA Channel Mask Register, Channels 7:0 Page 222 0D6h WO DMA Channel Mode Register, Channels 7:4 Page 222 0D8h WO DMA Clear Byte Pointer Command, Channels 7:4 Page 222 0DAh WO DMA Master Clear Command, Channels 7:4 Page 222 0DCh WO DMA Clear Mask Register Command, Channels 7:4 Page 222 0DEh WO DMA Write Mask Register Command, Channels 7:4 Page 222 DMA Page Registers (Table 4-28) 081h R/W DMA Channel 2 Low Page Register Page 223 082h R/W DMA Channel 3 Low Page Register Page 223 083h R/W DMA Channel 1 Low Page Register Page 223 087h R/W DMA Channel 0 Low Page Register Page 223 089h R/W DMA Channel 6 Low Page Register Page 223 08Ah R/W DMA Channel 7 Low Page Register Page 223 08Bh R/W DMA Channel 5 Low Page Register Page 223 08Fh R/W ISA Refresh Low Page Register Page 223 481h R/W DMA Channel 2 High Page Register Page 223 482h R/W DMA Channel 3 High Page Register Page 223 483h R/W DMA Channel 1 High Page Register Page 223 487h R/W DMA Channel 0 High Page Register Page 223 |
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