CS5530A datasheet(154/259 Pages) NSC

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154

Revision 1.1

Index 06h-07h

PCI Status Register (R/W)

Reset Value = 0280h

Detected Parity Error: This bit is set whenever a parity error is detected.

Write 1 to clear.

Signaled System Error: This bit is set whenever the CS5530A asserts SERR# active.

Write 1 to clear.

Received Master Abort: This bit is set whenever a master abort cycle occurs while the CS5530A is the master. A master

abort occurs when a PCI cycle is not claimed, except for special cycles.

Write 1 to clear.

Received Target Abort: This bit is set whenever a target abort is received while the CS5530A is the master for the PCI

cycle.

Write 1 to clear.

Signaled Target Abort: This bit is set whenever the CS5530A signals a target abort. This occurs when an address parity

error occurs for an address that hits in the active address decode space of the CS5530A.

Write 1 to clear.

10:9

DEVSEL# Timing (Read Only): These bits are always 01, as the CS5530A always responds to cycles for which it is an

active target with medium DEVSEL# timing. 00 = Fast; 01 = Medium; 10 = Slow; 11 = Reserved

Data Parity Detected: This bit is set when:

1) The CS5530A asserted PERR# or observed PERR# asserted.

2) The CS5530A is the master for the cycle in which a parity error occurred and the Parity Error bit is set (F0 Index 04h[6]

=1).

Write 1 to clear.

Fast Back-to-Back Capable (Read Only): As a target, the CS5530A is capable of accepting fast back-to-back

transactions. 0 = Disable; 1 = Enable.

This bit is always set to 1.

6:0

Reserved: Set to 0.

Index 08h

Device Revision ID Register (RO)

Reset Value = xxh

7:0

Device Revision ID (Read Only): Device revision level. 20h for revision A; 30h for revision B.

Index 09h-0Bh

PCI Class Code Register (RO)

Reset Value = 060100h

Index 0Ch

PCI Cache Line Size Register (R/W)

Reset Value = 00h

7:0

PCI Cache Line Size Register: This register sets the size of the PCI cache line, in increments of four bytes. For memory

write and invalidate cycles, the PCI cache line size must be set to 16 bytes (04h), and the Memory Write and Invalidate bit

must be set (F0 Index 04h[4] = 1).

Index 0Dh

PCI Latency Timer Register (R/W)

Reset Value = 00h

7:4

Reserved: Set to 0.

3:0

PCI Latency Timer Value: The PCI Latency Timer Register prevents system lockup when a slave does not respond to a

cycle that the CS5530A masters. If the value is set to 00h (default), the timer is disabled. If the timer is written with any other

value, bits [3:0] become the four most significant bytes in a timer that counts PCI clocks for slave response. The timer is

reset on each valid data transfer. If the timer expires before the next assertion of TRDY# is received, the CS5530A stops the

transaction with a master abort and asserts SERR#, if enabled to do so (F0 Index 04h[8] = 1).

Index 0Eh

PCI Header Type Register (RO)

Reset Value = 80h

7:0

PCI Header Type Register (Read Only): This register defines the format of this header. This header is of type format 0.

Additionally, bit 7 defines whether this PCI device is a multifunction device (bit 7 = 1) or not (bit 7 = 0).

Index 0Fh

PCI BIST Register (RO)

Reset Value = 00h

BIST Capable (Read Only): Is device capable of running a built-in self-test (BIST)? 0 = No; 1 = Yes,

Start BIST: Setting this bit to a one starts up a BIST on the device. The device resets this bit when the BIST has been com-

pleted. (Not supported.)

5:4

Reserved (Read Only)

3:0

BIST Completion Code (Read Only): Upon completion of the BIST, the completion code is stored in these bits. A comple-

tion code of zero indicates the BIST has successfully been completed. All other values indicate some type of BIST failure.

Index 10h-1Fh

Reserved

Reset Value = xxh

Index 20h-3Fh

Reserved

00h

Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

CS5530A Datasheet(PDF) 154 Page - National Semiconductor (TI)

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