CS5530A datasheet(160/259 Pages) NSC

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Revision 1.1

Index 80h

Power Management Enable Register 1 (R/W)

Reset Value = 00h

7:6

Reserved: Set to 0.

Codec SDATA_IN SMI: Allow AC97 codec to generate an SMI due to codec producing a positive edge on SDATA_IN.

0 = Disable; 1 = Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 87h/F7h[2].

Video Speedup: Any video activity, as decoded from the serial connection (PSERIAL register, bit 0) from the GX-series pro-

cessor disables clock throttling (via SUSP#/SUSPA# handshake) for a configurable duration when the system is power man-

aged using CPU Suspend modulation. 0 = Disable; 1 = Enable.

The duration of the speedup is configured in the Video Speedup Timer Count Register (F0 Index 8Dh). Detection of an

external VGA access (3Bxh, 3Cxh, 3Dxh and A000h-B7FFh) on the PCI bus is also supported. This configuration is non-

standard, but it does allow the power management routines to support an external VGA chip.

IRQ Speedup: Any unmasked IRQ (per I/O Port 021h/0A1h) or SMI disables clock throttling (via SUSP#/SUSPA# hand-

shake) for a configurable duration when the system is power managed using CPU Suspend modulation.

0 = Disable; 1 = Enable.

The duration of the speedup is configured in the IRQ Speedup Timer Count Register (F0 Index 8Ch).

Traps: Globally enable all power management device I/O traps. 0 = Disable; 1 = Enable.

This excludes the audio I/O traps. They are enabled at F3BAR+Memory Offset 18h.

Idle Timers: Globally enable all power management device idle timers. 0 = Disable; 1 = Enable.

Note, disable at this level does not reload the timers on the enable. The timers are disabled at their current counts.

This bit has no effect on the Suspend Modulation OFF/ON Timers (F0 Index 94h/95h), nor on the General Purpose (UDEFx)

Timers (F0 Index 88h-8Bh). This bit must be set for the command to trigger the SUSP#/SUSPA# feature to function (see F0

Index AEh).

Power Management: Global power management. 0 = Disable; 1 = Enabled.

This bit must be set (1) immediately after POST for some power management resources to function. Until this is done, the

command to trigger the SUSP#/SUSPA# feature is disabled (see F0 Index AEh) and all SMI# trigger events listed for

F0 Index 84h-87h are disabled. A ‘0’ in this bit does NOT stop the Idle Timers if bit 1 of this register is a ‘1’, but only prevents

them from generating an SMI# interrupt. It also has no effect on the UDEF traps.

Table 4-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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