SSM3525 datasheet(32/60 Pages) AD

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SSM3525

Data Sheet

Rev. A | Page 32 of 60

BOOTSTRAP CAPACITORS

The output stage of the SSM3525 uses a high-side N-channel

metal-oxide semiconductor (NMOS) driver, rather than a

P-channel metal-oxide semiconductor (PMOS) driver. To generate

the gate drive voltage for the high-side NMOS, a bootstrap

capacitor for each output terminal acts as a floating power supply

for the switching cycle. Use 0.22 μF capacitors to connect the

appropriate output pin (OUT±) to the bootstrap pin (BST±). For

example, connect a 0.22 μF capacitor between OUT+ and BST+

for bootstrapping the OUT+ pin. Similarly, connect another 0.22

μF capacitor between the OUT− and BST− pins for the OUT−

pin.

POWER SUPPLY DECOUPLING

To ensure high efficiency, low THD, and high PSRR, proper

power supply decoupling is necessary. Noise transients on the

power supply lines are short duration voltage spikes. These spikes

can contain frequency components that extend into the hundreds

of megahertz. The power supply input must be decoupled with

a low equivalent series inductance (ESL) and a low equivalent

series resistance (ESR) bulk capacitor larger than 220 µF. For high

frequency decoupling, place 1 µF capacitors as close as possible to

the PVDD pins of the device.

OUTPUT EMI FILTERING

Additional EMI filtering may be required when the speaker

traces and cables are long and present a significant capacitive

load that can create additional draw from the amplifier. Typical

power ferrites present a significant magnetic hysteresis cycle

that affects THD performance and are not recommended for

high performance designs. The NFZ series ferrite beads from

Murata are recommended. These ferrite beads provide a closed

hysteresis loop similar to an air coil with minimum impact on

performance. The ferrite beads with output current rating ≥4 A

rms, are recommended for this application. A 220 pF capacitor

can be added between the output of the filter and ground to

further attenuate high frequencies. Ensure the capacitor is

properly sized so as not to affect idle power consumption or

efficiency.

PCB COMPONENT PLACEMENT

Component selection and placement have great influence on

system performance, both measured and subjective. Proper

PVDD layout and decoupling is necessary to reach the specified

level of performance, particularly at the highest power levels.

The placement shown in Figure 79 ensures proper output stage

decoupling for each channel, for minimum supply noise and

maximum separation between channels. Additional bulk de-

coupling is necessary to reduce current ripple at low frequencies,

and can be shared between several amplifiers in a multichannel

solution.

PVDD DECOUPLING CAPACITOR

BST+ 0.22µF CAPACITOR

AVDD DECOUPLING CAPACITOR

IOVDD DECOUPLING CAPACITOR

Figure 79. Recommended Component Placement {should PVDD, AVDD, and IOVDD be AVDD, PVDD, IOVDD?

SSM3525 Datasheet(PDF) 32 Page - Analog Devices

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