SSM3525 datasheet(49/60 Pages) AD

49 / 60 page

Data Sheet

SSM3525

Rev. A | Page 49 of 60

PDM CONTROL REGISTER

Address: 0x21, Reset: 0x00, Name: PDM_CTRL

PDM Input and Output Mode

1: PDM us ed for input and output.

0: Norm al I2S/TDM operation.

PDM Sam ple Rate Selection

1: 2 MHz to 3 MHz clock in PDM m ode.

0: 4 MHz to 6 MHz clock in PDM m ode.

[7:5] RESERVED

[0] PDM_MODE (R/W)

[4] PDM_FS (R/W)

[3:1] RESERVED

Table 43. Bit Descriptions for PDM_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

[7:5]

RESERVED

Reserved.

0x0

PDM_FS

PDM Sample Rate Selection

0x0

R/W

4 MHz to 6 MHz clock in PDM mode.

2 MHz to 3 MHz clock in PDM mode.

[3:1]

RESERVED

Reserved.

0x0

PDM_MODE

PDM Input and Output Mode

0x0

R/W

Normal I2S/TDM operation.

PDM used for input and output.

SERIAL INTERFACE CONTROL 1 REGISTER

Address: 0x22, Reset: 0x21, Name: SAI_CTRL1

Drive Control for Unus ed BCLK Cycles

are driven low.

Unus ed BCLK cycles on SDATAO

are not driven (high-Z)

Unus ed BCLK cycles on SDATAO

Serial Interface Mode Selection

1: TDM/PCM m odes .

0: Stereo m odes (I2S or left jus tified)

Num ber of Bit Clocks per Chip in

TDM Mode

100: 64 BCLKs per Chip in TDM.

011: 48 BCLKs per Chip in TDM.

010: 32 BCLKs per Chip in TDM.

001: 24 BCLKs per Chip in TDM.

000: 16 BCLKs per Chip in TDM.

Serial Data Form at

edge.

Left Jus tified/no delay from FSYNC

edge.

I2S/delay by one bit clock from FSYNC

BCLK Polarity Control

1: Falling edge of BCLK regis ters SDATA.

0: Ris ing edge of BCLK regis ters SDATA.

FSYNC Mode Control

m odes .

m odes or 50% FSYNC m ode in TDM

High FSYNC is left channel in s tereo

TDM m odes .

m odes or puls ed FSYNC m ode in

Low FSYNC is left channel in s tereo

[7] SAI_DRV (R/W)

[0] SAI_MODE (R/W)

[6:4] TDM_BCLKS (R/W)

[1] SDATA_FMT (R/W)

[3] BCLK_POL (R/W)

[2] FSYNC_MODE (R/W)

Table 44. Bit Descriptions for SAI_CTRL1

Bits

Bit Name

Settings

Description

Reset

Access

SAI_DRV

Drive Control for Unused BCLK Cycles

0x0

R/W

Unused BCLK cycles on SDATAO are not driven (high-Z).

Unused BCLK cycles on SDATAO are driven low.

[6:4]

TDM_BCLKS

Number of Bit Clocks per Chip in TDM Mode. Any number of bit clock cycles per

FSYNC can be used in stereo modes (I2S or left justified) or in TDM mode with only

one chip. When in TDM mode and having multiple chips on the TDM bus, the

number of bit clocks per chip must be defined.

0x2

R/W

000

16 BCLKs per chip in TDM.

001

24 BCLKs per chip in TDM.

010

32 BCLKs per chip in TDM.

011

48 BCLKs per chip in TDM.

100

64 BCLKs per chip in TDM.

BCLK_POL

BCLK Polarity Control

0x0

R/W

Rising edge of BCLK registers SDATA.

Falling edge of BCLK registers SDATA.

SSM3525 Datasheet(PDF) 49 Page - Analog Devices

SSM3525 Datasheet(HTML) 49 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL