SSM3525 datasheet(27/60 Pages) AD

27 / 60 page

Data Sheet

SSM3525

Rev. A |Page 27 of 60

ANALOG AND DIGITAL GAIN

There are several selectable settings for the analog gain of the

system via the ANA_GAIN bits. These bits are designed to

provide optimal gain staging at various PVDD supply voltages.

There is also a digital gain/volume control in the DAC_VOL

to +24 dB.

PVDD (VBAT) SENSING

The SSM3525 contains an 8-bit ADC that measures the voltage of

the battery voltage (VBAT) supply. The battery voltage information is

stored in Register 0x13 as an 8-bit unsigned format. The ADC

input range is fixed internally as 4 V to 18 V. To convert the

hexidecimal value to the voltage value, use the following steps:

1. Convert the hex value to decimal. For example, if the

hexadecimal value is 0xA9, the decimal value is 169.

2. Calculate the voltage using the following equation:

Voltage = 4 V + 14 V × Decimal Value/255

With a decimal value of 169,

Voltage = 4 V + 14 V × 169/255 = 13.278 V

This data can be output on the SDATAO pin along with V/I

sense data or read via the VBAT register over the control

interface, as previously mentioned.

FAULTS AND LIMITER STATUS REPORTING

The SSM3525 offers comprehensive protections against the

faults at the outputs and reporting to help with system design.

The faults listed in Table 16 are reported using the status registers.

Table 16. Register 0x11 Faults

Fault Type

Flag Set

Condition

Status Reported

5 V Regulator or AVDD

Undervoltage (UV)

5 V regulator

voltage at VREG/

AVDD < 3.6 V

UVLO_VREG

PVDD Undervoltage

When PVDD < 3.6V

UVLO_PVDD

Limiter/Gain Reduction

Engage

Limiter engaged

Bit 5, LIM_EG

Clipping

DAC clipping

Bit 4, CLIP

Output Overcurrent

(OC)

Output current >

6 A peak

Bit 3, AMP_OC

Die Overtemperature

(OT)

Die temperature >

145°C

Bit 2, OTF

Die Overtemperature

Warning (OTW)

Die temperature >

117°C

Bit 4, OTW

Battery Voltage >

VBAT_INF

Battery voltage

PVDD > VBAT_INF

Bit 0, BAT_WARN

The faults listed in Table 16 are reported in Register 0x11 and

can be read via I2C by the microcontroller in the system.

In the event of a fault occurrence, how the device reacts to the

faults can be controlled by using Register 0x10.

Table 17. Register 0x10 Fault Recovery

Fault Type

Flag Set Condition

Status Reported

OTW

The amount of gain

reduction applied if

there is an OTW

OTW_GAIN

Manual

Recovery

Use to attempt manual

recovery in case of a

fault event

MRCV

Autorecovery

Attempts

When autorecovery

from faults is used, set

the number of attempts

using this bit

MAX_AR

Recovery can be

automatic or manual

ARCV_UV

Die OT

Recovery can be

automatic or manual

ARCV_OT

Recovery can be

automatic or manual

ARCV_OC

When the automatic recovery mode is set, the device attempts

to recover itself after the fault event and, in case the fault

persists, the device sets the fault again. This process repeats

until the fault is resolved.

When using the manual recovery mode, the device shuts down

and the recovery must be attempted using the system

microcontroller.

LIMITER AND BATTERY TRACKING THRESHOLD

CONTROL

The SSM3525 contains an output limiter that can limit the peak

output voltage of the amplifier. The limiter works on the rms

and peak value of the signal. The limiter threshold, slope, attack

rate, and release rate are programmable using Register 0x08,

disabled using LIM_EN, Bits[1:0] in Register 0x08.

The threshold at which the output starts limiting is determined

by the LIM_THRES register setting, in Register 0x09, Bits[7:3].

When the ouput signal level exceeds the set threshold level, the

limiter activates and limits the signal level to the set limit. Below

the set threshold, the output level is not affected. The limiter

threshold can be set from 2 VPEAK to 16 VPEAK.

The limiter threshold can be set above the maximum output

voltage of the amplifier. In this case, the limiter allows maximum

peak output; the output can clip depending on the power supply

voltage and not the limiter.

The limiter threshold can be set as fixed or to vary with the

battery voltage via the VBAT_TRACK bit (Register 0x08, Bit 2).

When set to fixed, the limiter threshold is fixed and does not

vary with battery voltage. The threshold can be set from 2 VPEAK to

16 VPEAK using the LIM_THRES bit (see Figure 71).

When set to a variable threshold, the SSM3525 monitors the

VBAT supply and automatically adjusts the limiter threshold

based on the VBAT supply voltage.

SSM3525 Datasheet(PDF) 27 Page - Analog Devices

SSM3525 Datasheet(HTML) 27 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL