SSM3525 datasheet(24/60 Pages) AD

24 / 60 page

SSM3525

Data Sheet

Rev. A | Page 24 of 60

POWER-DOWN MODES

The SSM3525 can be powered down by several methods.

Setting the SPWDN bit to 1 in Register 0x20 fully powers down

the device except for the I2C interface. Individual blocks can

also be powered on or off via the block level power-down

controls.

For lowest power shutdown, the SSM3525 also contains a clock

loss detection circuit that monitors the BCLK input clock.

When no BCLK is present, the device automatically powers

down all internal circuitry to its lowest power state. When

BCLK returns, the device automatically powers up following its

usual power sequence.

There is an optional auto power-down feature when using

I2S/TDM: the device enters a lower power state when 2048

consecutive zero input samples are received. The device auto-

matically powers back up from this state once a single nonzero

value sample is received. Only the I2C and digital audio input

blocks are active.

OUTPUT CURRENT SENSING

The SSM3525 uses an integrated sense resistor (50 mΩ typical)

to determine the output current flowing to the load. The voltage

across this sense resistor is proportional to the load current and

sent to a 1-bit ADC running nominally at 128 × fs. The sense

voltage can be output in I2S/TDM format in I2S/TDM mode or via

the PDM interface in PDM mode. The output of this ADC can

also be downsampled using digital filtering. The data is 16 bits,

twos complement and in signed fraction format. This

downsampled signal is at an 8 kHz to 192 kHz sample rate. It

can be output on the SDATAO pin.

To set a different sample rate for both current and voltage

sensing, use the SNS_FS bit in Register 0x05.

OUTPUT VOLTAGE SENSING

The output voltage level is monitored at the OUT± pins and

sent to a 1-bit analog to digital converter running nominally at

128 × fs. This can be output in PDM format in PDM mode or

via the PDM interface in PDM mode. The output of this ADC is

can also be downsampled using digital filtering. This

downsampled signal at 8 kHz to 192 kHz sample rate is output

on the digital audio interface. The data is 16 bits twos

complement and in signed fraction format. It can be output on

the SDATAO pin.

TEMPERATURE SENSOR

The SSM3525 contains an 8-bit ADC that measures the die

temperature of the device and is enabled via the TEMP_PWDN bit

in Register 0x20. After the sensor is enabled, the temperature

sense value can be read via the I2C in Register 0x12 in an 8-bit,

unsigned format.

The ADC input range is fixed internally from −60°C to +195°C.

To convert the hexadecimal value to the temperature (Celsius)

value, use the following steps:

1. Convert the hexadecimal value to decimal and then

subtract 60. For example, if the hexadecimal value is 0x54,

the decimal value is 84.

2. Calculate the temperature using the following equation:

Temperature = Decimal Value − 60

3. With a decimal value of 84, Temperature = 84 − 60 = 24°C

PCM DIGITAL AUDIO SERIAL INTERFACE

The SSM3525 includes a standard serial audio interface that is

slave only and used when in I2C mode. The interface is capable

of receiving and transmitting I2S, left justified, pulse code

modulated (PCM), or TDM formatted data.

There is an input interface for sending audio to the DAC and

amplifier and an output interface for the sense, temperature,

and automatic gain control (AGC) gain data. These interfaces

share the same FSYNC and BCLK signals.

Provide a BCLK signal to the SSM3525 for correct operation. The

BCLK signal must have a minimum frequency of 2.048 MHz.

The BCLK signal internally clocks the device. The BCLK rate is

auto detected, but the sampling frequency must be known to

the device. At the 32 kHz to 48 kHz sample rate, the supported

BCLK rates are 50, 64, 100, 128, 150, 192, 200, 250, 256, 384,

400, 500, 512, 768, 800, and 1024 times the sample rate.

The serial interfaces have three main operating modes. Stereo

modes, typically I2S or left justified, are used when there are one

or two chips on the interface bus. TDM modes are more flexible

and can support up to 32 chips on the bus. These mode selections

can be set via the I2C interface with the SAI_MODE bit.

The SAI_DRV bit setting determines the state of the SDATAO

pin during the unused bit clock cycles. When the SAI_DRV bit

is set to 1, the SDATAO pin is driven to logic low or not driven

(high-Z) when set to 0. If using multiple chips on the serial

interface bus, SAI_DRV bit must be set to 0.

STEREO (I2S/LEFT JUSTIFIED) OPERATING MODE

Stereo modes use both edges of the FSYNC signal to determine

placement of data. Stereo mode is enabled when SAI_MODE =

0 and the I2S or left justified format is determined by the

SDATA_FMT bit.

The I2S or left justified formats accepts any number of BCLK

cycles per FSYNC cycle.

The six placement control registers (Address 0x24 to Address 0x29)

determine placement of input and output data. Odd numbered

placement control registers determine the order on the left channel

and even number on the right channel.

Sample rates from 8 kHz to 192 kHz are accepted.

SSM3525 Datasheet(PDF) 24 Page - Analog Devices

SSM3525 Datasheet(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL