SSM3525 datasheet(7/60 Pages) AD

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Data Sheet

SSM3525

Rev. A |Page 7 of 60

Software master power-down indicates the clocks are turned off. Auto power-down indicates there is no dither or zero input signal with

clocks on; the device enters soft power-down after 2048 cycles of zero input values. Quiescent indicates triangular dither with zero input

signal. All specifications are typical, with a 48 kHz sample rate, unless otherwise noted.

Table 2. Power Supply Current Consumption1

Edge Rate

Control

Mode

No Load

4 Ω + 15 μH

8 Ω +33 μH

Unit

IPVDD

IIOVDD IAVDD

IPVDD

IIOVDD IAVDD

IPVDD

IIOVDD AVDD

5 V

12 V 17 V 1.8 V 5 V 5 V 12 V 17 V 1.8 V 5 V 5 V 12 V 17 V 1.8 V 5 V

Normal

Software master power-down 0.09 0.09 0.09 8.01 3.24 0.09 0.09 0.09 8.01 3.24 0.09 0.09 0.09 8.01 3.24

μA

Quiescent (all ADCs on)

1.73 3.43 4.49 0.992 5.14 1.96 3.55 4.61 0.994 5.26 1.67 3.29 4.49 0.995 5.14

Quiescent (all ADCs off)

1.74 3.44 4.51 0.817 3.28 1.96 3.54 4.61 0.816 3.44 1.67 3.29 4.49 0.82 3.34

Software master power-down 0.09 0.09 0.09 8.01 N/A 0.09 0.09 0.09 8.01 N/A 0.09 0.09 0.09 8.01 N/A

μA

Quiescent (all ADCs on)

6.86 8.56 9.65 0.995 N/A 6.81 8.61 10.21 0.998 N/A 6.83 8.51 9.79 0.996 N/A

Quiescent (all ADCs off)

5.04 6.73 7.86 0.821 N/A 4.98 6.75 8.44 0.766 N/A 5.01 6.69 7.96 0.817 N/A

Low EMI

Software master power-down 0.09 0.09 0.09 8.01 3.24 0.09 0.09 0.09 8.01 3.24 0.09 0.09 0.09 8.01 3.24

μA

Quiescent (all ADCs on)

1.663 3.35 4.48 0.991 5.08 1.6 3.35 4.68 0.994 5.21 1.59 3.28 4.48 0.996 5.09

Quiescent (all ADCs off)

1.663 3.35 4.58 0.823 3.28 1.6 3.37 4.71 0.819 3.41 1.59 3.25 4.48 0.819 3.27

Software master power-down 0.09 0.09 0.09 8.01 N/A 0.09 0.09 0.09 8.01 N/A 0.09 0.09 0.09 8.01 N/A

μA

Quiescent (all ADCs on)

6.73 8.46 9.8 0.998 N/A 6.71 8.56 10.02 0.995 N/A 6.72 8.45 9.61 0.992 N/A

Quiescent (all ADCs off)

4.91 6.62 7.97 0.823 N/A 4.89 6.74 8.19 0.816 N/A 4.89 6.58 7.81 0.821 N/A

N/A means not applicable.

Table 3. Digital Input/Output

Parameter

Min

Typ

Max

Unit

HIGH INPUT VOLTAGE (VIH)

BCLK, FSYNC, SDATAI, and SDATAO

0.7 × IOVDD

1.98

SCL and SDA

0.7 × IOVDD

5.5

LOW INPUT VOLTAGE (VIL)

BCLK, FSYNC, SDATAI, SDATAO, SDA, SCL

−0.3

0.3 × IOVDD

ADDR

−0.3

IOVDD + 0.3

INPUT LEAKAGE

HIGH (IIH)

µA

LOW (IIL)

µA

INPUT CAPACITANCE

OUTPUT DRIVE STRENGTH (SDATAO)

TIMING SPECIFICATIONS

Table 4. I2C Port Timing

Parameter

Min

Max

Unit

Description

I2C PORT

fSCL

MHz

SCL frequency

tSCLH

0.26

µs

SCL high

tSCLL

0.5

µs

SCL low

tSCS

0.26

µs

Setup time; relevant for repeated start condition

tSCH

0.26

µs

Hold time; after this period, the first clock is generated

tDS

Data setup time

tSCR

120

SCL rise time

tSCF

120

SCL fall time

tSDR

120

SDA rise time

tSDF

120

SDA fall time

tBFT

0.5

µs

Bus-free time (time between stop and start)

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