SSM3525 datasheet(26/60 Pages) AD

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SSM3525

Data Sheet

Rev. A | Page 26 of 60

8 BITS/16 BITS/24 BITS

BCLK

FSYNC

DAC_SDATAI

Figure 66. Basic Timing Diagram of Placements in I2S Stream

VOLTAGE

16 BCLKs

BATTERY

CURRENT

DAC INPUT

8 BCLKs

BCLK

FSYNC

DAC_SDATAI

DAC_SDATAO

Figure 67. Standard I2S Data Placement Timing Diagram

DAC DATA 1

VSENSE 1

BCLK

FSYNC

DAC_SDATAI

DAC_SDATAO

32 BCLKS

DAC DATA 2

ISENSE 2

Figure 68. TDM Serial Interface Format

Table 13. 8-Bit Status Sense Output Format (STATUS Register)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

UVLO_VREG

UVLO_PVDD

LIM_EG

CLIP

AMP_OC

OTF

OTW

BAT_WARN

Table 14. 8-Bit V/I Marker and Status Sense Output Format (STATUS Register)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

1 = VSENSE, 0 = ISENSE

UVLO_PVDD

LIM_EG

CLIP

AMP_OC

OTF

OTW

BAT_WARN

SDATA

FSYNC

BCLK

Figure 69. SDATA Output in PDM Mode

PDM OPERATING MODE

By setting the PDM_MODE bit in Register 0x21 to 1, the 1-bit

PDM data from the sense ADCs can be output directly on

SDATAO, and the DAC can be driven with 1-bit PDM data on

SDATAI. In this case, a 2.048 MHz to 6.144MHz CLK must be

provided on the BCLK pin.

PDM input data is latched on both edges of the clock. The

FSYNC pin state determines which channel (left or right) is

sent to the DAC.

Table 15. FSYNC Settings for PDM Mode

SDATA Input

FSYNC Pin Configuration

Use L Channel Data

Connect to IOVDD

Use R Channel Data

Connect to GND

PDM data is output on both edges of the clock. The current

sense ADC data is output when BCLK is high, and the voltage

sense ADC data is output when BCLK is low. Refer to Table 12

and Figure 69.

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