SSM3525 datasheet(16/60 Pages) AD

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SSM3525

Data Sheet

Rev. A | Page 16 of 60

PVDD (V)

1% THD + N

10% THD + N

Figure 30. Output Power vs. PVDD, RL = 4 Ω, Analog Gain = 12.6

PVDD (V)

1% THD + N

10% THD + N

Figure 31. Output Power vs. PVDD, RL = 4 Ω,

Analog Gain = 16

100

0.5

1.0

1.5

2.0

3.0

2.5

3.5

OUTPUT POWER (W)

NORMAL EMI

LOW EMI

Figure 32. Efficiency vs. Output Power (POUT), RL = 4 Ω, No Ferrite Bead (FB)

and 220 pF Capacitor, PVDD = 5 V, Analog Gain = 6.3

100

OUTPUT POWER (W)

NORMAL EMI

LOW EMI

Figure 33. Efficiency vs. Output Power (POUT), RL = 4 Ω, No Ferrite Bead (FB)

and 220pF Capacitor, PVDD = 7 V, Analog Gain = 8.9

100

OUTPUT POWER (W)

NORMAL EMI

LOW EMI

Figure 34. Efficiency vs. Output Power (POUT), RL = 4 Ω, No Ferrite Bead (FB)

and 220 pF Capacitor, PVDD = 12 V, Analog Gain = 12.6

100

OUTPUT POWER (W)

NORMAL EMI

LOW EMI

Figure 35. Efficiency vs. Output Power (POUT), RL = 4 Ω, No Ferrite Bead (FB)

and 220 pF Capacitor, PVDD = 17 V, Analog Gain = 16

SSM3525 Datasheet(PDF) 16 Page - Analog Devices

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