SSM3525 datasheet(23/60 Pages) AD

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Data Sheet

SSM3525

Rev. A |Page 23 of 60

THEORY OF OPERATION

OVERVIEW

The SSM3525 Class D audio amplifier features a filterless

modulation scheme that reduces the external component count,

conserving board space and reducing system cost. The SSM3525

does not require an output filter; it relies on the inherent

inductance of the speaker coil and the natural filtering of the

speaker and human ear to recover the audio component of the

square wave output. Most Class D amplifiers use some variation

of pulse-width modulation (PWM), but the SSM3525 uses sigma-

delta (Σ-Δ) modulation to determine the switching pattern of

the output devices, resulting in a number of important benefits:

Σ-Δ modulators do not produce a sharp peak with many

harmonics in the amplitude modulation (AM) broadcast band,

as PWMs often do. Σ-Δ modulation reduces the amplitude of

spectral components at high frequencies, reducing EMI

emission that can otherwise be radiated by speakers and long

cable traces. Due to the inherent spread spectrum nature of Σ-Δ

modulation, the need for oscillator synchronization is eliminated

for designs incorporating multiple SSM3525 amplifiers.

The SSM3525 also integrates overcurrent and temperature

protection and a thermal warning with optional programmable

gain reduction.

The SSM3525 contains output voltage and current sensing with

digitization. It also has a temperature sensor and a supply voltage

sensor for the PVDD pin. The PVDD pin is typically connected to

the battery or power supply in the system.

The SSM3525 supports two main modes of operation with

control and data supplied through the I2C and TDM/I2S ports

(see Table 12).

POWER SUPPLIES

The power supply pins on the SSM3525 are as follows:

•

PVDD, the power supply, is used for the output stage.

•

AVDD is the analog supply used for the input stage,

modulator, power stage gate drive, and other blocks. It can

be generated internally by the integrated linear regulator.

Alternatively, if higher system efficiency is needed, connect

the AVDD pin to an external 5 V supply in the system.

•

If the REG_EN control register is set to 1, the internal

regulator is enabled; otherwise, an external 5 V supply is

required.

•

IOVDD is the digital supply voltage for the serial audio

interface and internal digital circuitry. It must be supplied

externally.

ADDR PIN SETUP AND CONTROL

The SSM3525 supports I2C control. The ADDR pin can be set

to four different levels: pulled to GND, pulled up to IOVDD via a

47 kΩ resistor, pulled down to ground via a 47 kΩ resistor, or

left open. The state of the ADDR pin determines the I2C device

address. By default in I2C mode, the device uses the BCLK, FSYNC,

SDATAI, and SDATAO pins for TDM/I2S data. Alternatively, the

device can be set to receive and transmit PDM data by setting

the PDM_MODE register bit field. See Table 12 for setting up the

desired mode.

Table 11. I2C Address Selection

ADDR Pin Connection

Control Port Mode

IOVDD Range (V)

I2C Address

GND

I2C

1.2 to 1.8

0x24

Pull Down

I2C

1.2 to 1.8

0x25

Open

I2C

1.2 to 1.8

0x26

Pull Up

I2C

1.2 to 1.8

0x27

IOVDD

Reserved

Not applicable

Table 12. Serial Port Mode Setup for I2S, TDM, and PDM

Serial Port

Mode

IOVDD Range

Description

Pin Usage

BCLK Pin

SDATAO Pin

FSYNC Pin

SDATAI Pin

I2S/TDM

1.2 V to 1.8 V

Sets the part into default I2S/TDM mode

Bit clock

input

Sense data

output

I2S/TDM

format

Frame clock

input

Data input

I2S/TDM

format

PDM

1.2 V to 1.8 V

Set the PDM_MODE bit to 1 in Register 0x21,

use FSYNC pin for setting the left/right channel

PDM clock

input

Sense data

output PDM

format

GND (left

channel) and

IOVDD (right

channel)

Data input

PDM format

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