SIM6800M datasheet(20/52 Pages) SANKEN

20 / 52 page

SIM6800M Series

SIM6800M-DSE Rev.1.5

SANKEN ELECTRIC CO., LTD

Jul. 18, 2018

http://www.sanken-ele.co.jp/en

VCC1

VB1B

VB3

COM2

VCC2

COM1

VBB

VB2

VCC

CBOOT1

CBOOT3

CBOOT2

MIC

HO1

HO2

HO3

DBOOT1

DBOOT2

DBOOT3

RBOOT1

RBOOT2

RBOOT3

VDC

Figure 12-1.

Bootstrap Circuit

Figure 12-2 shows an internal level-shifting circuit. A

high-side output signal, HOx, is generated according to

an input signal on the HINx pin. When an input signal

on the HINx pin transits from low to high (rising edge),

a “Set” signal is generated. When the HINx input signal

transits from high to low (falling edge), a “Reset” signal

is generated. These two signals are then transmitted to

the high-side by the level-shifting circuit and are input to

the SR flip-flop circuit. Finally, the SR flip-flop circuit

feeds an output signal, Q (i.e., HOx).

Figure 12-3 is a timing diagram describing how noise

or other detrimental effects will improperly influence the

level-shifting process. When a noise-induced rapid

voltage drop between the VBx and output pins (U, V or

W1; hereafter “VBx–HSx”) occurs after the Set signal

generation, the next Reset signal cannot be sent to the

SR flip-flop circuit. And the state of an HOx signal stays

logic high (or “H”) because the SR flip-flop does not

respond. With the HOx state being held high (i.e., the

high-side transistor is in an on-state), the next LINx

signal turns on the low-side transistor and causes a

simultaneously-on condition, which may result in

critical damage to the IC. To protect the VBx pin against

such a noise effect, add a bootstrap capacitor, CBOOTx, in

each phase. CBOOTx must be placed near the IC, and be

connected between the VBx and HSx pins with a

minimal length of traces. To use an electrolytic capacitor,

add a 0.01 μF to 0.1 μF bypass capacitor, C

Px, in parallel

near these pins used for the same phase.

HINx

Input

logic

Pulse

generator

COM1

Set

Reset

HOx

VBx

HSx

Figure 12-2.

Internal Level-shifting Circuit

HINx

Set

Reset

VBx–HSx

VBS(OFF)

VBS(ON)

Stays logic high

Figure 12-3.

Waveforms at VBx–HSx Voltage Drop

12.2.3

VCC1 and VCC2

These are the power supply pins for the built-in

control IC. The VCC1 and VCC2 pins must be

externally connected on a PCB because they are not

internally connected. To prevent malfunction induced by

supply ripples or other factors, put a 0.01 μF to 0.1 μF

ceramic capacitor, CVCC, near these pins. To prevent

damage caused by surge voltages, put an 18 V to 20 V

Zener diode, DZ, between the VCCx and COMx pins.

Voltages to be applied between the VCCx and COMx

pins should be regulated within the recommended

operational range of VCC, given in Section 2.

VCC1

COM2

VCC2

COM1

VCC

MIC

CVCC

Figure 12-4.

VCCx Pin Peripheral Circuit

12.2.4

COM1 and COM2

These are the logic ground pins for the built-in control

IC. The COM1 and COM2 pins should be connected

externally on a PCB because they are not internally

connected. Varying electric potential of the logic ground

can be a cause of improper operations. Therefore,

connect the logic ground as close and short as possible

to shunt resistors, RSx, at a single-point ground (or star

ground) which is separated from the power ground (see

Figure 12-5).

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