SIM6800M datasheet(24/52 Pages) SANKEN

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SIM6800M Series

SIM6800M-DSE Rev.1.5

SANKEN ELECTRIC CO., LTD

Jul. 18, 2018

http://www.sanken-ele.co.jp/en

activated and sets an HOx signal to logic low. When the

voltage between the VBx and HSx pins increases to the

Logic Operation Start Voltage (VBS(ON), 10.5 V) or more,

the IC releases the UVLO_VB condition. Then, the HOx

signal becomes logic high at the rising edge of the first

input command after the UVLO_VB release. The FO

pin does not transmit any fault signals during the

UVLO_VB operation. In addition, the VBx pin has an

internal UVLO_VB filter of about 3 μs, in order to

prevent noise-induced malfunctions.

12.3.3.2. Undervoltage Lockout for

Low-side Power Supply

(UVLO_VCC)

Figure 12-11 shows operational waveforms of the

undervoltage lockout operation for low-side power

supply (i.e., UVLO_VCC).

When the VCC2 pin voltage decreases to the Logic

Operation Stop Voltage (VCC(OFF), 11.0 V) or less, the

UVLO_VCC circuit in the corresponding phase gets

activated and sets both of HOx and LOx signals to logic

low. When the VCC2 pin voltage increases to the Logic

Operation Start Voltage (VCC(ON), 11.5 V) or more, the

IC releases the UVLO_VCC condition. Then, the IC

resumes the following transmissions: an LOx signal

according to an LINx pin input command; an HOx

signal according to the rising edge of the first HINx pin

input command after the UVLO_VCC release. During

the UVLO_VCC operation, the FO pin becomes logic

low and sends fault signals. In addition, the VCC2 pin

has an internal UVLO_VCC filter of about 3 μs, in order

to prevent noise-induced malfunctions.

About 3 µs

LINx

HINx

VCC2

HOx

LOx

VCC(OFF)

VCC(ON)

LOx responds to input signal.

UVLO_VCC

operation

Figure 12-11.

UVLO_VCC Operational Waveforms

12.3.4

Overcurrent Limit (OCL)

The overcurrent limit (OCL) is a protection against

relatively low overcurrent conditions. Figure 12-12

shows an internal circuit of the OCP and OCL pins;

Figure 12-13 shows OCL operational waveforms.

When the OCP pin voltage increases to the Current

Limit Reference Voltage (VLIM, 0.6500 V) or more, and

remains in this condition for a period of the Current

Limit Blanking Time (tBK(OCP), 2

μs) or longer, the OCL

circuit is activated. Then, the OCL pin goes logic high.

During the OCL operation, the gate logic levels of the

low-side transistors respond to an input command on the

LINx pin. If the OCL and SD pins are connected on a

PCB, the high-side transistors can be turned off even

during the OCL operation. The SD pin has an internal

filter of about 3.3 μs (typ.).

When the OCP pin voltage falls below VLIM (0.6500

V), the OCL pin logic level becomes low. After the OCL

pin logic has become low, the high-side transistors

remain turned off until the first low-to-high transition on

an HINx input signal occurs (i.e., rising edge triggering).

OCP

COM2

200 k

2 k

OCL

0.65 V

Filter

200 k

2 k

Figure 12-12.

Internal Circuit of OCP and OCL Pins

LINx

HINx

OCP

HOx

LOx

OCL

(SD)

VLIM

tBK(OCP)

3.3 µs (typ.)

HOx restarts at

positive edge after

OCL release.

Figure 12-13.

OCL Operational Waveforms

(OCL = SD)

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