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AD9510 Datasheet(PDF) 33 Page - Analog Devices

Part # AD9510
Description  1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
PDF  56 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9510 Datasheet(HTML) 33 Page - Analog Devices

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Data Sheet
AD9510
Rev. C | Page 33 of 56
Example 1:
Set the Divide Ratio = 2
HIGH_CYCLES = 0
LOW_CYCLES = 0
Divide Ratio = (0 + 1) + (0 + 1) = 2
Example 2:
Set Divide Ratio = 8
HIGH_CYCLES = 3
LOW_CYCLES = 3
Divide Ratio = (3 + 1) + (3 + 1) = 8
Note that a Divide Ratio of 8 can also be obtained by setting:
HIGH_CYCLES = 2
LOW_CYCLES = 4
Divide Ratio = (2 + 1) + (4 + 1) = 8
Although the second set of settings produces the same divide
ratio, the resulting duty cycle is not the same.
Setting the Duty Cycle
The duty cycle and the divide ratio are related. Different
divide ratios have different duty cycle options. For example, if
Divide Ratio = 2, the only duty cycle possible is 50%. If the
Divide Ratio = 4, the duty cycle can be 25%, 50%, or 75%.
The duty cycle is set by
Duty Cycle = (HIGH_CYCLES + 1)/((HIGH_CYCLES + 1)
+ (LOW_CYCLES + 1))
See Table 18 for the values for the available duty cycles for each
divide ratio.
Table 18. Duty Cycle and Divide Ratio
Divide Ratio
Duty Cycle (%)
Address 0x48 to
Address 0x56
LO[7:4]
HI[3:0]
2
50
0
0
3
67
0
1
3
33
1
0
4
50
1
1
4
75
0
2
4
25
2
0
5
60
1
2
5
40
2
1
5
80
0
3
5
20
3
0
6
50
2
2
6
67
1
3
6
33
3
1
6
83
0
4
6
17
4
0
7
57
2
3
7
43
3
2
7
71
1
4
7
29
4
1
7
86
0
5
7
14
5
0
8
50
3
3
8
63
2
4
8
38
4
2
8
75
1
5
8
25
5
1
8
88
0
6
8
13
6
0
9
56
3
4
9
44
4
3
9
67
2
5
Divide Ratio
Duty Cycle (%)
Address 0x48 to
Address 0x56
LO[7:4]
HI[3:0]
9
33
5
2
9
78
1
6
9
22
6
1
9
89
0
7
9
11
7
0
10
50
4
4
10
60
3
5
10
40
5
3
10
70
2
6
10
30
6
2
10
80
1
7
10
20
7
1
10
90
0
8
10
10
8
0
11
55
4
5
11
45
5
4
11
64
3
6
11
36
6
3
11
73
2
7
11
27
7
2
11
82
1
8
11
18
8
1
11
91
0
9
11
9
9
0
12
50
5
5
12
58
4
6
12
42
6
4
12
67
3
7
12
33
7
3
12
75
2
8
12
25
8
2



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