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AD9510

Data Sheet

Rev. C | Page 14 of 56

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SDIO (WHEN INPUT)

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

2.7

Output Logic 0 Voltage

0.4

TIMING

Clock Rate (SCLK, 1/tSCLK)

MHz

Pulse Width High, tPWH

Pulse Width Low, tPWL

SDIO to SCLK Setup, tDS

SCLK to SDIO Hold, tDH

SCLK to Valid SDIO and SDO, tDV

CSB to SCLK Setup and Hold, tS, tH

CSB Minimum Pulse Width High, tPWH

FUNCTION PIN

Table 9.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

INPUT CHARACTERISTICS

FUNCTION pin has 30 kΩ internal pull-down resistor;

normally, hold this pin high; do not leave unconnected

Logic 1 Voltage

2.0

Logic 0 Voltage

0.8

Logic 1 Current

110

µA

Logic 0 Current

µA

Capacitance

RESET TIMING

Pulse Width Low

SYNC TIMING

Pulse Width Low

1.5

High speed clock cycles

High speed clock is CLK1 or CLK2, whichever is being used

for distribution

STATUS PIN

Table 10.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT CHARACTERISTICS

When selected as a digital output (CMOS), there are other modes in

which the STATUS pin is not CMOS digital output; see Figure 37

Output Voltage High (VOH)

2.7

Output Voltage Low (VOL)

0.4

MAXIMUM TOGGLE RATE

100

MHz

Applies when PLL mux is set to any divider or counter output, or PFD up/

down pulse; also applies in analog lock detect mode; usually debug mode

only; beware that spurs can couple to output when this pin is toggling

ANALOG LOCK DETECT

Capacitance

On-chip capacitance, used to calculate RC time constant for analog lock

detect readback; use a pull-up resistor

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