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Data Sheet

AD9510

Rev. C | Page 15 of 56

POWER

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER-UP DEFAULT MODE POWER DISSIPATION

550

600

Power-up default state, does not include power

dissipated in output load resistors; no clock

Power Dissipation

1.1

All outputs on; four LVPECL outputs at 800 MHz, 4 LVDS

out at 800 MHz; does not include power dissipated in

external resistors

Power Dissipation

1.3

All outputs on; four LVPECL outputs at 800 MHz, 4 CMOS

out at 62 MHz (5 pF load); does not include power

dissipated in external resistors

Power Dissipation

1.5

All outputs on; four LVPECL outputs at 800 MHz, 4 CMOS

out at 125 MHz (5 pF load); does not include power

dissipated in external resistors

Full Sleep Power-Down

Maximum sleep is entered by setting Register 0x0A[1:0] =

01b and Register 0x58[4] = 1b; this powers off the PLL BG

and the distribution BG references; does not include

power dissipated in terminations

Power-Down (PDB)

Set the FUNCTION pin for PDB operation by setting

power dissipated in terminations

POWER DELTA

CLK1, CLK2 Power-Down

Divider, DIV 2 − 32 to Bypass

For each divider

LVPECL Output Power-Down (PD2, PD3)

For each output; does not include dissipation in

termination (PD2 only)

LVDS Output Power-Down

110

For each output

CMOS Output Power-Down (Static)

For each output; static (no clock)

CMOS Output Power-Down (Dynamic)

115

150

190

For each CMOS output, single-ended; clocking at

62 MHz with 5 pF load

CMOS Output Power-Down (Dynamic)

125

165

210

For each CMOS output, single-ended; clocking at

125 MHz with 5 pF load

Delay Block Bypass

Versus delay block operation at 1 ns fs with maximum

delay, output clocking at 25 MHz

PLL Section Power-Down

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