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AD9510 Datasheet(PDF) 16 Page - Analog Devices |
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AD9510 Datasheet(HTML) 16 Page - Analog Devices |
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16 / 56 page ![]() AD9510 Data Sheet Rev. C | Page 16 of 56 TIMING DIAGRAMS Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode Figure 3. LVPECL Timing, Differential Figure 4. LVDS Timing, Differential Figure 5. CMOS Timing, Single-Ended, 3 pF Load CLK1 tCMOS tCLK1 tLVDS tPECL DIFFERENTIAL LVPECL 80% 20% tRP tFP DIFFERENTIAL LVDS 80% 20% tRL tFL SINGLE-ENDED CMOS 3pF LOAD 80% 20% tRC tFC |
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