AD9510 datasheet(30/56 Pages) AD

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AD9510

Data Sheet

Rev. C | Page 30 of 56

Phase Frequency Detector (PFD) and Charge Pump

The PFD takes inputs from the R counter and the N counter

(N = BP + A) and produces an output proportional to the

phase and frequency difference between them. Figure 36 is a

simplified schematic. The PFD includes a programmable delay

element that controls the width of the antibacklash pulse. This

pulse ensures that there is no dead zone in the PFD transfer

function and minimizes phase noise and reference spurs. Two

bits in Register 0x0D[1:0] control the width of the pulse.

Figure 36. PFD Simplified Schematic and Timing (In Lock)

Antibacklash Pulse

The PLL features a programmable antibacklash pulse width that

is set by the value in Register 0x0D[1:0]. The default antiback-

lash pulse width is 1.3 ns (Register 0x0D[1:0] = 00b) and

normally does not need to be changed. The antibacklash pulse

eliminates the dead zone around the phase-locked condition

and thereby reduces the potential for certain spurs that can be

impressed on the VCO signal.

STATUS Pin

The output multiplexer on the AD9510 allows access to various sig-

nals and internal points on the chip at the STATUS pin. Figure 37

shows a block diagram of the STATUS pin section. The function

of the STATUS pin is controlled by Register 0x8[5:2].

PLL Digital Lock Detect

The STATUS pin can display two types of PLL lock detect:

digital (DLD) and analog (ALD). Whenever digital lock detect

is desired, the STATUS pin provides a CMOS level signal, which

can be active high or active low.

The digital lock detect has one of two time windows, as selected

by Register 0x0D[5]. The default (Register 0x0D[5] = 0b) requires

the signal edges on the inputs to the PFD to be coincident within

9.5 ns to set the DLD true, which then must separate by at least

15 ns to give DLD = false.

The other setting (Register 0x0D[5] = 1) makes these coinci-

dence times 3.5 ns for DLD = true and 7 ns for DLD = false.

The DLD can be disabled by writing 1 to Register 0x0D[6].

If the signal at REFIN goes away while DLD is true, the DLD

does not necessarily indicate loss of lock. See the Loss of

Reference section for more information.

Figure 37. STATUS Pin Circuit CLK1 Clock Input

D1 Q1

CLR1

R DIVIDER

D2 Q2

CLR2

N DIVIDER

DOWN

CHARGE

PUMP

GND

PROGRAMMABLE

DELAY

ANTIBACKLASH

PULSE WIDTH

OFF (LOW) (DEFAULT)

DIGITAL LOCK DETECT (ACTIVE HIGH)

N DIVIDER OUTPUT

DIGITAL LOCK DETECT (ACTIVE LOW)

R DIVIDER OUTPUT

ANALOG LOCK DETECT (N-CHANNEL OPEN DRAIN)

A COUNTER OUTPUT

PRESCALER OUTPUT (NCLK)

PFD UP PULSE

PFD DOWN PULSE

LOSS OF REFERENCE (ACTIVE HIGH)

TRISTATE

ANALOG LOCK DETECT (P-CHANNEL OPEN DRAIN)

LOSS OF REFERENCE OR LOCK DETECT (ACTIVE HIGH)

LOSS OF REFERENCE OR LOCK DETECT (ACTIVE LOW)

LOSS OF REFERENCE (ACTIVE LOW)

PLL MUX CONTROL

0x08[5:2]

SYNC DETECT ENABLE

0x58[0]

SYNC

DETECT

GND

STATUS

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