AD9547 datasheet(59/106 Pages) AD

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Data Sheet

AD9547

Rev. G | Page 59 of 106

I/O PROGRAMMING REGISTERS

The register map spans an address range from 0x0000 through

0x0E3F (0 to 3647, decimal). Each address provides access to one

byte (eight bits) of data. Each individual register is identified by its

four-digit hexadecimal address (for example, Register 0x0A10). In

some cases, a group of addresses collectively define a register (for

example, the IRQ mask register consists of Register 0x0209,

0x020D, Register 0x020E, Register 0x020F, and Register 0x0210).

In general, when a group of registers defines a control parameter,

the LSB of the value resides in the D0 position of the register with

the lowest address. The bit weight increases from right to left, from

the lowest register address to the highest register address. For

example, the default value of the incremental phase lock offset step

size register (Address 0x0314 to Address 0x0315) is the 16-bit

hexadecimal number, 0x03E8 (not 0xE803). Note that the

EEPROM storage sequence registers (Address 0x0E10 to Address

0x0E3F) are an exception to this convention (see the EEPROM

Instructions section).

BUFFERED/ACTIVE REGISTERS

There are two broad categories of registers on the AD9547;

buffered and active (see Figure 66). Buffered registers need an I/O

update to apply their contents to the internal device functions. In

contrast, active registers do not require an I/O update to transfer

data between the buffered registers and the internal device

functions. In operation, the user programs as many buffered

registers as desired and then issues an I/O update. The I/O update

is performed by writing to Register 0x0005, Bit 0 = 1 (or by the

external application of the necessary logic level to one of the

multifunction pins previously programmed as an I/O update

input). The contents of the buffered registers that are connected

directly to the internal device functions affect those functions

immediately. The contents of buffered registers that connect to

active registers do not affect the internal device functions until the

I/O update event occurs.

An L in the Opt column of the register map indicates an active

(or live) register. An S or a C in the Opt column of the register

map identifies a buffered register. An S entry means that the I/O

update signal to the active register is synchronized with the serial

port clock or with an input signal driving one of the multifunction

pins. On the other hand, a C entry means that the I/O update signal

to the active register is synchronized with a clock signal derived

from the internal system clock (fS/32), as shown in Figure 66.

When reading back a register that has both buffered and active

contents, Register 0x0004, Bit 0 can be used to select whether to

read back the buffered or active contents. Read-back of the active

contents occurs when Register 0x0004, Bit 0= 0, whereas readback

of the buffered contents occurs when Register 0x0004, Bit 0 = 1.

Note that a read-only active register requires an I/O update before

its contents can be read.

FROM

MULTIFUNCTION

PIN LOGIC

SERIAL

CONTROL

PORT

fS/32

EDGE

DETECT

CS/SDA

SCLK/SCL

SDIO

SDO

Figure 66. Buffered and Active Registers

AUTOCLEARING REGISTERS

An A in the Opt column of the register map identifies an auto-

clearing register. Typically, the active value for an autoclearing

the internal device logic upon completion of the prescribed action.

Read and write access to the registers may be restricted, depending

on the register in question, the source and direction of access,

and the current state of the device. Each register can be classified

into one or more access types. When more than one type applies,

the most restrictive condition that applies at that time is used.

When access is denied to a register, all attempts to read the register

return a 0 byte, and all attempts to write to the register are ignored.

Access to nonexistent registers is handled in the same way as for

a denied register.

Regular Access

Registers with regular access do not fall into any other category.

Both read and write access to registers of this type can be from

the serial port or the EEPROM controller. However, only one of

these sources can have access to a register at any given time (access

is mutually exclusive). When the EEPROM controller is active,

either in load or store mode, it has exclusive access to the registers.

Read-Only Access

An R in the Opt column of the register map identifies read-only

registers. Access is available at all times, including when the

EEPROM controller is active.

Exclusion from EEPROM Access

An E in the Opt column of the register map identifies a register

with contents that are inaccessible to the EEPROM. That is, the

contents of this type of register cannot be transferred directly to

the EEPROM or vice versa. Note that read-only registers (R) are

inaccessible to the EEPROM, as well.

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