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AD9547 Datasheet(PDF) 94 Page - Analog Devices |
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AD9547 Datasheet(HTML) 94 Page - Analog Devices |
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94 / 106 page  AD9547 Data Sheet Register 0x0A0E to Register 0x0A10—Reference Validation Override Controls Table 130. Force Validation Timeout1 Address Bit Bit Name Description 0x0A0E [7:4] Unused Unused. 3 Force Timeout BB Setting this bit emulates timeout of the validation timer for Reference BB. This is an autoclearing bit. 2 Force Timeout B Setting this bit emulates timeout of the validation timer for Reference B. This is an autoclearing bit. 1 Force Timeout AA Setting this bit emulates timeout of the validation timer for Reference AA. This is an autoclearing bit. 0 Force Timeout A Setting this bit emulates timeout of the validation timer for Reference A. This is an autoclearing bit. 1 All bits in this register are autoclearing. Table 131. Reference Monitor Override1 Address Bit Bit Name Description 0x0A0F [7:4] Unused Unused. 3 Ref Mon Override BB Overrides the reference monitor REF fault signal for Reference BB (default = 0, not overridden). 2 Ref Mon Override B Overrides the reference monitor REF fault signal for Reference B (default = 0, not overridden). 1 Ref Mon Override AA Overrides the reference monitor REF fault signal for Reference AA (default = 0, not overridden). 0 Ref Mon Override A Overrides the reference monitor REF fault signal for Reference A (default = 0, not overridden). 1 All bits in this register are autoclearing. Table 132. Reference Monitor Bypass1 Address Bit Bit Name Description 0x0A10 [7:4] Unused Unused. 3 Ref Mon Bypass BB Bypasses the reference monitor for Reference BB (default = 0, not bypassed). 2 Ref Mon Bypass B Bypasses the reference monitor for Reference B (default = 0, not bypassed). 1 Ref Mon Bypass AA Bypasses the reference monitor for Reference AA (default = 0, not bypassed). 0 Ref Mon Bypass A Bypasses the reference monitor for Reference A (default = 0, not bypassed). 1 All bits in this register are autoclearing. CLOCK PART SERIAL ID (REGISTER 0x0C00 TO REGISTER 0x0C07) User programmable EEPROM ID registers. Table 133. User Defined Identification Registers Address Bits Bit Name Description 0x0C00 [7:0] User scratch pad[7:0] User programmable EEPROM ID registers. These registers enable users to write a unique code of their choosing to keep track of revisions to the EEPROM register loading. It has no effect on part operation. The default EEPROM storage sequence must be altered to include these registers. See the Programming the EEPROM to Include a Clock Part ID section. 0 = default. 0x0C01 [7:0] User scratch pad[15:8] 0x0C02 [7:0] User scratch pad[23:16] 0x0C03 [7:0] User scratch pad[31:24] 0x0C04 [7:0] User scratch pad[39:32] 0x0C05 [7:0] User scratch pad[47:40] 0x0C06 [7:0] User scratch pad[55:48] 0x0C07 [7:0] User scratch pad[63:56] Rev. G | Page 94 of 106 |
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