AD9547 datasheet(91/106 Pages) AD

91 / 106 page

Data Sheet

AD9547

Table 120. Loop Mode

Address

Bit

Bit Name

Description

0x0A01

Unused

Unused.

User holdover

Force the device into holdover mode.

0 (default) = normal operation.

1 = force device into holdover mode.

The device functions as though all input references are faulted.

User free run

Force the device into free-run mode.

0 (default) = normal operation.

1 = force device into free-run mode.

The free-running frequency tuning word register (Address 0x0300 to Address 0x0305)

specifies the DDS output frequency.

Note that, when user free run is set, it overrides user holdover.

[4:3]

User selection mode

Select the operating mode of the reference switching state machine.

00 (default) = automatic mode. The fully automatic priority-based algorithm selects the

active reference (Bits[1:0] are ignored).

01 = fallback mode. The active reference is the user reference (Bits[1:0]) as long as it is valid.

Otherwise, use the fully automatic priority-based algorithm to select the active reference.

10 = holdover mode. The active reference is the user reference (Bits[1:0]) as long as it is

valid. Otherwise, enter holdover mode.

11 = manual mode. The active reference is always the user reference (Bits[1:0]). When using

manual mode, be sure that the reference declared as the user reference (Bits[1:0]) is

programmed for manual reference-to-profile assignment in the appropriate manual

reference profile selection register (Address 0x0503 and Address 0x0506).

Unused

Unused. Write a 0 to this bit.

[1:0]

User reference selection

Input reference when user selection mode = 01, 10, or 11.

00 (default) = Input Reference A.

01 = Input Reference AA.

10 = Input Reference B.

11 = Input Reference BB.

Table 121. Cal/Sync

Address

Bit

Bit Name

Description

0x0A02

[7:2]

Unused

Unused.

Sync distribution

Setting this bit (default = 0) initiates synchronization of the clock distribution output. When

this bit = 1, the clock distribution output stalls. Synchronization occurs on the 1 to 0 transition of

this bit.

Calibrate SYSCLK

A 0 to 1 transition of this bit (default = 0), followed by an IO_UPDATE, initiates an internal

calibration of the SYSCLK PLL (assuming it is enabled). The calibration routine automatically

selects the proper VCO frequency band and signal amplitude. The internal system clock stalls

during the calibration procedure, disabling the device until the calibration is complete (a few

milliseconds). If the user wishes to recalibrate the SYSCLK PLL and this bit is already set to 1,

the user must first write a 0 to this bit, issue an IO_UPDATE, write a 1 to this bit, and issue

another IO_UPDATE.

Rev. G | Page 91 of 106

AD9547 Datasheet(PDF) 91 Page - Analog Devices

AD9547 Datasheet(HTML) 91 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL