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AD9547 Datasheet(PDF) 100 Page - Analog Devices

Part # AD9547
Description  Dual/Quad Input Network Clock Generator/Synchronizer
PDF  106 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9547 Datasheet(HTML) 100 Page - Analog Devices

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AD9547
Data Sheet
Table 155. EEPROM Storage Sequence for Profile 2 and Profile 3 Settings
Address
Bit
Bit Name
Description
0x0E25
[7:0]
Profile 2 and Profile 3
The default value of this register is 0x63, which the controller interprets as a data instruction. Its
decimal value is 99, which tells the controller to transfer 100 bytes of data (99 + 1), beginning at
the address specified by the next two bytes. The controller stores 0x63 in the EEPROM and
increments the EEPROM address pointer.
0x0E26
[7:0]
Profile 2 and Profile 3
The default value of these two registers is 0x0680. Note that Register (0x0E26 and Register 0x0E27
are the most significant and least significant bytes of the target address, respectively. Because
the previous register contains a data instruction, these two registers define a starting address
(in this case, 0x0680). The controller stores 0x0680 in the EEPROM and increments the EEPROM
pointer by 2. It then transfers 100 bytes from the register map (beginning at Address 0x0680) to
the EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and one checksum
byte). The 99 bytes transferred correspond to the Profile 2 and Profile 3 parameters in the
register map.
0x0E27
[7:0]
Table 156. EEPROM Storage Sequence for Profile 4 and Profile 5 Settings
Address
Bit
Bit Name
Description
0x0E28
[7:0]
Profile 4 and Profile 5
The default value of this register is 0x63, which the controller interprets as a data instruction.
Its decimal value is 99, which tells the controller to transfer 100 bytes of data (99 + 1)
beginning at the address specified by the next two bytes. The controller stores 0x63 in the
EEPROM and increments the EEPROM address pointer.
0x0E29
[7:0]
Profile 4 and Profile 5
The default value of these two registers is 0x0700. Note that Register
0x0E29 and Register 0x0E2A
are the most significant and least significant bytes of the target address, respectively. Because
the previous register contains a data instruction, these two registers define a starting address
(in this case, 0x0700). The controller stores 0x0700 in the EEPROM and increments the EEPROM
pointer by 2. It then transfers 100 bytes from the register map (beginning at Address 0x0700)
to the EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and one
checksum byte). The 99 bytes transferred correspond to the Profile 4 and Profile 5 parameters
in the register map.
0x0E2A
[7:0]
Table 157. EEPROM Storage Sequence for Profile 6 and Profile 7 Settings
Address
Bit
Bit Name
Description
0x0E2B
[7:0]
Profile 6 and Profile 7
The default value of this register is 0x63, which the controller interprets as a data instruction.
Its decimal value is 99, this tells the controller to transfer 100 bytes of data (99 + 1) beginning
at the address specified by the next two bytes. The controller stores 0x63 in the EEPROM and
increments the EEPROM address pointer.
0x0E2C
[7:0]
Profile 6 and Profile 7
The default value of these two registers is 0x0780. Note that Register 0x0E2C and Register 0x0E2D
are the most significant and least significant bytes of the target address, respectively. Because
the previous register contains a data instruction, these two registers define a starting address
(in this case, 0x0780). The controller stores 0x0780 in the EEPROM and increments the EEPROM
pointer by 2. It then transfers 100 bytes from the register map (beginning at Address 0x0780)
to the EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and one
checksum byte). The 99 bytes transferred correspond to the Profile 6 and Profile 7 parameters
in the register map.
0x0E2D
[7:0]
0x0E2E
[7:0]
I/O update
The default value of this register is 0x80, which the controller interprets as an I/O update
instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.
Rev. G | Page 100 of 106



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