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AD9547 Datasheet(PDF) 101 Page - Analog Devices

Part # AD9547
Description  Dual/Quad Input Network Clock Generator/Synchronizer
PDF  106 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9547 Datasheet(HTML) 101 Page - Analog Devices

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Data Sheet
AD9547
Table 158. EEPROM Storage Sequence for Operational Control Settings
Address
Bit
Bit Name
Description
0x0E2F
[7:0]
Operational controls
The default value of this register is 0x10, which the controller interprets as a data
instruction. Its decimal value is 16, this tells the controller to transfer 17 bytes of data
(16 + 1) beginning at the address specified by the next two bytes. The controller stores
0x10 in the EEPROM and increments the EEPROM address pointer.
0x0E30
[7:0]
Operational controls
The default value of these two registers is 0x0A00. Note that Register 0x0E30 and Register
0x0E31 are the most significant and least significant bytes of the target address,
respectively. Because the previous register contains a data instruction, these two
registers define a starting address (in this case, 0x0A00). The controller stores 0x0A00 in
the EEPROM and increments the EEPROM pointer by 2. It then transfers 17 bytes from
the register map (beginning at Address 0x0A00) to the EEPROM and increments the
EEPROM address pointer by 18 (17 data bytes and one checksum byte). The 17 bytes
transferred correspond to the operational controls parameters in the register map.
0x0E31
[7:0]
0x0E32
[7:0]
I/O update
The default value of this register is 0x80, which the controller interprets as an I/O
update instruction. The controller stores 0x80 in the EEPROM and increments the
EEPROM address pointer.
Table 159. EEPROM Storage Sequence for End of Data
Address
Bits
Bit Name
Description
0x0E33
[7:0]
End of data
The default value of this register is 0xFF, which the controller interprets as an end
instruction. The controller stores this instruction in the EEPROM, resets the EEPROM
address pointer, and enters an idle state.
0x0E34 to
0x0E3F
Continuation of user
scratch pad area
This area is unused in the default configuration and is available for additional EEPROM
storage sequence commands. Note that the EEPROM storage sequence should always
end with either an end of data or pause command.
Rev. G | Page 101 of 106



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