LPC47M192 datasheet(188/228 Pages) SMSC

188 / 228 page

SMSC DS – LPC47M192

Page 188

Rev. 03/30/05

DATASHEET

NAME/DEFAULT

OFFSET

(hex)

DESCRIPTION

VID Register

Default:

Bits[7:4]=0000

Bits[3:0]=VID3-

VID0 on HVCC

POR

and

Initialization

Bits[6:0] are

Read Only;

Bit[7] is (R/W)

Bits[3:0] VID[3:0]

The VID[3:0] inputs from Pentium/PRO power supplies to indicate

the operating voltage (e.g. 1.5V to 2.9V).

Bits[6:4] Reserved

Bit[7] RESET# Enable

0= Enables A0 pin for lowest order programmable bit of SMBus

address (Default)

1= Enables the RESET# pin output function

VID4 Register

Default:

Bits[7]=1,

Bits[6:1]=0

Bit[0]=VID4

HVCC POR and

Initialization

(R)

Bit[0] VID 4

VID 4 Input (If selected).

Bits[6:1] Reserved

Bit[7] Reserved1

Test

Mode

Default = 0x00

on HVCC POR

and Initialization

(R/W)

Bit[0] selects the ADC test mode. The default for this bit is zero,

which deactivates ADC test mode.

Bit[1] selects the digital test mode. The default for this bit is zero,

which deactivates digital test mode.

Bit[2] selects the external clock test mode. The default for this bit

is zero, which deactivates external oscillator clock test mode.

Bit[3] selects either 8 or 1 averaging for the ADC test mode. The

default for this bit is zero, which sets the averaging to 8 for the

ADC test mode. A one in this bit selects no averaging.

Bit[4] selects the oscillator clock to be muxed out on the VID2 pin.

The default for this bit is zero, which deactivates mux oscillator

clock test mode.

Bits[7:5] are used by the analog block for test purposes. These

three

bits

4Ah

are

muxed

out

pins

dig_test_an_pad[2:0]. These bits are also used to mux out either

the SDA line or the SCLK line to the VID3 pin. If bits[7:5] are ‘001’,

then the SDA line is muxed out onto the VID3 pin. If bits[7:5] are

‘010’, then the SCLK line is muxed out onto the VID3 pin.

Error

Debug

Default = 0x00

on HVCC POR

and Initialization

(R)

Bit[0] indicates that no NACK was generated by the host during

either a read byte protocol or a receive byte protocol.

Bit[1] indicates a read or a write was attempted to an invalid

Bit[2] indicates a write to a read only register was attempted

Bit[3] indicates a receive byte protocol was attempted when the

address pointer register pointed to the 00h location. This is the

default register location on power on reset. As noted in the “Bus

Protocols” section of the “Hardware Monitoring Interface” section,

the Internal Address register should be set up with a valid address

location by either a send byte protocol or a write byte protocol

after power-on-reset, before the receive byte protocol.

Bit[4] indicates an invalid slave address was detected.

Bit[5] indicates a premature stop was detected.

Bit[6] indicates an error was detected during the SMBus Receive

Byte Protocol Response to an ARA.

Bit[7] is reserved.

LPC47M192 Datasheet(PDF) 188 Page - SMSC Corporation

LPC47M192 Datasheet(HTML) 188 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL