D17133CS datasheet(140/289 Pages) NEC

140 / 289 page

CHAPTER 13

PERIPHERAL HARDWARE

125

(2) Error in Starting Counting from the Count Halt State

The count register of the 8-bit timer counter is cleared to zero by setting (to 1) the TMRES flag; however,

the scaler for generating the count pulse from the system clock is not reset. When the TMEN flag is set (to

1) to start the counting from the count halt status, the timing of the first count varies as follows depending

on whether the count pulse is started from the low level or from the high level.

When started from the high level: the next rising edge is the first count

When started from the low level: the count starting point is the first count

Therefore, only the first count after the counting is started generates an error of –0.5 to –1.5 counts during

the time until the identity signal is issued. An example of counting when 1 is set for the modulo register is

shown below.

Figure 13-5. Error in Starting Counting from the Count Halt State

(a) When the count pulse is stated from the high level (error: –0.5 to –1 count)

Counting start (TMEN = 1

←0)

Match signal output

1 to 1.5 count

2 counts

Match signal output

Count pulse

Count register

D17133CS Datasheet(PDF) 140 Page - NEC