D17133CS datasheet(141/289 Pages) NEC

141 / 289 page

CHAPTER 13

PERIPHERAL HARDWARE

126

(b) When the count pulse is started from the low level (error: –1 to –1.5 counts)

In the example above, the identity signal is generated every 2 counts; however, only for the first count, the

identity signal is issued for 1.5 counts maximum and for 0.5 count minimum (error: –0.5 to –1.5 counts).

As the timer is in use even for generation of the oscillation stability wait time, the error margin above occurs

even to this oscillation stability wait time.

13.1.7 Reading Count Register Values

(1) Reading Counter values

The counter values of count register are read at the same time via DBF (data buffer) using the GET instruction.

The count register values of timer are assigned to peripheral address 02H.

Count register values of timer can be read into DBF by using the GET instruction. During execution of the

GET instruction, timer count register stops count operation and a count value is retained. When a count pulse

enters the timer in use during execution of the GET instruction, the count is retained.

After execution of the GET instruction, the count register increments by one and continues counting.

The scheme prevents miscounting as long as two or more count pulses are not input in one instruction cycle,

even when the GET instruction is executed during timer operation.

Counting start (TMEN = 1

←0)

Match signal output

2 counts

Match signal output

0.5 to 1count

Count pulse

Count register

D17133CS Datasheet(PDF) 141 Page - NEC