D17133CS datasheet(145/289 Pages) NEC

145 / 289 page

CHAPTER 13

PERIPHERAL HARDWARE

130

13.1.9 Timer Resolution and Maximum Setting Time

Table 13-1 shows the timer resolution in each source clock and maximum setting time.

Table 13-1. Timer Resolution and Maximum Setting Time

Mode Register

Timer

TMCK1

TMCK0

Resolution

Maximum Setting Time

µs

8.192 ms

µs

1.024 ms

256

µs

65.536 ms

INT pin Note 2

approx. 61.1

µs

approx. 15.6 ms

approx. 7.64

µs

approx. 1.9 ms

approx. 489

µs

approx. 125 ms

INT pin Note 2

128

µs

32.768 ms

µs

4.096 ms

1.024 ms

262.144 ms

INT pin Note 2

512

µs

131.072 ms

µs

16.384 ms

4.096 ms

1.048576 s

INT pin Note 2

Notes

1. The guaranteed frequency range of oscillation for the

µPD17120/17132/17P132 is fCC=400 kHz to

2.4 MHz.

2. High/low level width of INT pin is 10

µs (MIN.) when VDD=4.5 to 5.5 V, and 50 µs (MIN.) when VDD=2.7

to 5.5 V. Refer to Data Sheet for detailed information.

System Clock

At 8 MHz Note1

At 4.19 MHz Note1

At 2 MHz

At 500 kHz

D17133CS Datasheet(PDF) 145 Page - NEC

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