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D17133CS Datasheet(PDF) 154 Page - NEC |
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D17133CS Datasheet(HTML) 154 Page - NEC |
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154 / 289 page ![]() CHAPTER 13 PERIPHERAL HARDWARE 139 Figure 13-15. Serial Interface Control Register (1/2) RF: 1AH Read = R, write = W SIOCK1 0 0 1 1 SIOCK0 0 1 0 1 Serial Clock Selection External clock (SCK pin) fX/16 fX/128 fX/1024 Function Selection of the P0D1/SO pin Serial data output (SO pin) Input port (P0D1 pin) Confirmation of Shift Register Operation Status (at Reading) The shift register is in the stop status. The shift register is operating. Start and Stop of Serial Transmission (at Writing) Forced termination of the shift register. Disables intermediate restart. Start of shift register operation • At internal clock selection Starts operating internal devided signal of a system clock (fX) as a serial clock • At external clock selection Starts operation in synchronization with an SCK pin falling edge. SIOHIZ 0 1 SIOTS 0 1 Remark SIOTS is automatically cleared to 0 when serial transmission is completed. Read/write Initial value when reset Bit 3 SIOTS 0 Bit 2 SIOHIZ 0 Bit 1 SIOCK1 0 Bit 0 SIOCK0 0 R/W SIOTS 0 1 |
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