D17133CS datasheet(162/289 Pages) NEC

162 / 289 page

CHAPTER 14

INTERRUPT FUNCTIONS

147

14.2 HARDWARE COMPONENTS OF THE INTERRUPT CONTROL CIRCUIT

The flags of the interrupt control circuit are explained below.

14.2.1 Interrupt Request Flag (IRQ

×××) and the Interrupt Enable Flag (IP×××)

The interrupt request flag (IRQ

×××) is set to 1 when an interrupt request occurs. When interrupt handling is

executed, the flag is automatically cleared to 0.

An interrupt enable flag (IP

×××) is provided for each interrupt request flag. If the flag is 1, an interrupt is enabled.

If it is 0, the interrupt is disabled.

14.2.2 EI/DI Instruction

The EI/DI instruction is used to determine whether an accepted interrupt is to be executed.

If the EI instruction is executed, INTE for enabling interrupt reception is set. Since the INTE flag is not registered

in the register file, flag status cannot be checked by instructions.

The DI instruction clears the INTE flag to 0 and disables all interrupts.

At reset the INTE flag is cleared to 0 and all interrupts are disabled.

Table 14-2. Interrupt Request Flag and Interrupt Enable Flag

Interrupt

Request Flag

Enagle Flag

IRQ

Set by edge detection of an INT pin input signal.

A detection edge is selected by IEGMD0 or

IEGMD1.

IRQTM

Set by a match signal from timer.

IPTM

IRQSIO

Set by a serial data transmission end signal from

IPSIO

the serial interface.

Signal for Setting the Interrupt Request Flag

D17133CS Datasheet(PDF) 162 Page - NEC