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ADV7330 Datasheet(PDF) 7 Page - Analog Devices |
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ADV7330 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 76 page ![]() REV. B ADV7330 –7– t9 t11 CLKIN t10 t12 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 HSYNC_I/P VSYNC_I/P BLANK_I/P CONTROL INPUTS Y0 Y1 Y2 Y3 Y4 Y5 Y7–Y0 C7–C0 t14 HSYNC_O/P VSYNC_O/P BLANK_O/P CONTROL OUTPUTS t13 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME Figure 1. HD/PS 4:2:2 Input Mode (HD: Input Mode 010) (PS: Input Mode 001) CLKIN Y7–Y0 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME t11 t12 t13 t14 t11 t12 t9 t10 Cb0 Y0 Y1 Crxxx Yxxx Cr0 HSYNC_I/P VSYNC_I/P BLANK_I/P CONTROL INPUTS HSYNC_O/P VSYNC_O/P BLANK_O/P CONTROL OUTPUTS Figure 2. PS 4:2:2 1 × 8-Bit Interleaved at 27 MHz Hsync/Vsync Input Mode (Input Mode 100) |
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