ADV7330 datasheet(9/76 Pages) AD

9 / 76 page

REV. B

ADV7330

–9–

Y7–Y0

CLKIN

t11

t14

t13

t10

t12

YCb

IN MASTER/SLAVE

MODE

IN SLAVE MODE

HSYNC_I/P

VSYNC_I/P

BLANK_I/P

CONTROL

INPUTS

HSYNC_O/P

VSYNC_O/P

BLANK_O/P

CONTROL

OUTPUTS

Figure 6. 8-Bit SD Pixel Input Mode (Input Mode 000)

Y7–Y0

CLKIN

t11

t14

t13

t10

t12

C7–C0

Cb0

Cr0

Cb2

Cr2

IN MASTER/SLAVE

MODE

IN SLAVE MODE

HSYNC_I/P

VSYNC_I/P

BLANK_I/P

CONTROL

INPUTS

HSYNC_O/P

VSYNC_O/P

BLANK_O/P

CONTROL

OUTPUTS

Figure 7. 16-Bit SD Pixel Input Mode (Input Mode 000)

HSYNC_I/P

VSYNC_I/P

BLANK_I/P

Y7–Y0

C7–C0

Cb0

Cr0

Cr1

Cb1

A = 16 CLK CYCLES FOR 525p

A = 12 CLK CYCLES FOR 626p

A = 44 CLK CYCLES FOR 1080i @ 30Hz, 25Hz

A = 70 CLK CYCLES FOR 720p

AS RECOMMENDED BY STANDARD

B (MIN) = 122 CLK CYCLES FOR 525p

B (MIN) = 132 CLK CYCLES FOR 625p

B (MIN) = 236 CLK CYCLES FOR 1080i @ 30Hz, 25Hz

B (MIN) = 300 CLK CYCLES FOR 720p

Figure 8. HD 4:2:2 Input Timing Diagram

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