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ADV7330 Datasheet(PDF) 18 Page - Analog Devices |
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ADV7330 Datasheet(HTML) 18 Page - Analog Devices |
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18 / 76 page ![]() REV. B –18– ADV7330 NOTES 1When set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. When set to 1, the field/line counters are free running and wrap around when external sync signals indicate so. SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset Values 12h HD Mode Register 3 00 0 0 Clk Cycle 00h 00 11 Clk Cycle 01 0 2 Clk Cycles 01 13 Clk Cycles 10 0 4 Clk Cycles 00 0 0 Clk Cycle 00 1 1 Clk Cycle 01 0 2 Clk Cycles 01 13 Clk Cycles 10 0 4 Clk Cycles HD CGMS 0 Disabled 1 Enabled HD CGMS CRC 0 Disabled 1 Enabled 13h HD Mode Register 4 HD Cr/Cb Sequence 0 Cb after Falling Edge of HSYNC 4Ch 1 Cr after Falling Edge of HSYNC Reserved 00 must be written to this bit. Reserved 0 0 must be written to this bit. Sinc Filter on DAC A, B, C 0 Disabled 1 Enabled Reserved 0 0 must be written to this bit. HD Chroma SSAF 0 Disabled 1 Enabled Reserved 1 HD Double Buffering 0 Disabled 1 Enabled 14h HD Mode Register 5 HD Timing Reset xA low-high-low transition resets the internal HD timing counters. 00h 00 30 Hz/2200 Total Samples/Line 01 25 Hz/2640 Total Samples/Line Reserved 00 0 0 must be written to these bits. HD Vsync/Field Input 0 Field Input 1 Vsync Input Lines/Frame 1 0 Update Field/Line Counter 1 Field/Line Counter Free Running 15h HD Mode Register 6 Reserved 0 0 must be written to this bit. 00h HD RGB Input 0 Disabled 1 Enabled HD Sync on PrPb 0 Disabled 1 Enabled HD Color DAC Swap 0 DAC E = Pr; DAC F = Pb 1 DAC E = Pb; DAC F = Pr HD Gamma Curve A/B 0 Gamma Curve A 1 Gamma Curve B HD Gamma Curve Enable 0 Disabled 1 Enabled HD Adaptive Filter Mode 0 Mode A 1 Mode B HD Adaptive Filter Enable 0 Disabled 1 Enabled HD Y Delay with respect to falling edge of HSYNC HD Color Delay with respect to falling edge of HSYNC 1080i Frame Rate |
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