ADV7330 datasheet(14/76 Pages) AD

14 / 76 page

REV. B

–14–

ADV7330

SDATA

SCLOCK

START ADRR R/

W ACK SUBADDRESS ACK

DATA

ACK

STOP

1–7

Figure 13. Bus Data Transfer

WRITE

SEQUENCE

READ

SEQUENCE

SLAVE ADDR

A(S)

SUBADDR

A(S)

DATA

A(S)

DATA

A(S)

SLAVE ADDR

A(S)

SUBADDR

A(S) S

SLAVE ADDR

A(S)

DATA

A(M)

A(M) P

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A(S) = NO-ACKNOWLEDGE BY SLAVE

A(M) = NO-ACKNOWLEDGE BY MASTER

LSB = 0

LSB = 1

Figure 14. Write and Read Sequence

Stop and start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of sequence

with normal read and write operations, they cause an immediate

jump to the idle condition. During a given SCL high period, the

user should issue only one start condition, one stop condition,

or a single stop condition followed by a single start condition.

If an invalid subaddress is issued by the user, the ADV7330 will

not issue an acknowledge and will return to the idle condition.

If in auto-increment mode the user exceeds the highest subaddress,

the following action will be taken:

1. In read mode, the highest subaddress register contents will

continue to be output until the master device issues a no

acknowledge. This indicates the end of a read. A no acknowl-

edge condition is when the SDA line is not pulled low on the

ninth pulse.

2. In write mode, the data for the invalid byte will not be loaded

into any subaddress register, a no acknowledge will be issued

by the ADV7330, and the part will return to the idle condition.

Before writing to the subcarrier frequency registers, it is a require-

ment that the ADV7330 reset at least once after power-up.

The four subcarrier frequency registers must be updated starting

with subcarrier frequency register 0 through subcarrier frequency

last subcarrier frequency register byte has been received by

the ADV7330.

Figure 13 illustrates an example of data transfer for a write

sequence and the start and stop conditions. Figure 14 shows

bus write and read sequences.

The MPU can write to or read from all of the registers of the

ADV7330 except the subaddress registers that are write-only

registers. The subaddress register determines which register the

next read or write operation accesses. All communications with

the part go through the bus start with an access to the subaddress

target address, which then increments to the next address until

a stop command on the bus is performed.

The following tables describe the functionality of each register.

All registers can be read from as well as written to, unless other-

wise stated.

Subaddress Register (SR7–SR0)

The communications register is an 8-bit write-only register. After

the part has been accessed over the bus and a read/write operation

is selected, the subaddress is set up. The subaddress register

determines to/from which register the operation takes place.

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