ADV7330 datasheet(27/76 Pages) AD

27 / 76 page

REV. B

ADV7330

–27–

INPUT CONFIGURATION

Note that the ADV7330 defaults to progressive scan 54 MHz

mode on power-up. Address(01h): Input Mode = 011

Standard Definition

Address(01h): Input Mode = 000

The 8-bit multiplexed input data is input on Pins Y7–Y0, with Y0

being the LSB. Input standards supported are ITU-R BT.601/656.

In 16-bit input mode the Y pixel data is input on Pins Y7–Y0

and CrCb data on Pins C7–C0.

Input sync signals are optional and are input on the

VSYNC_I/P,

HSYNC_I/P, and BLANK_I/P pins.

MPEG2

DECODER

VSYNC_I/P

HSYNC_I/P

BLANK_I/P

CLKIN

Y[7:0]

27MHz

YCrCb

ADV7330

Figure 16. SD Input Mode

Progressive Scan or HDTV Mode

Address(01h): Input Mode 001 or 010, Respectively

YCrCb progressive scan, HDTV, or any other HD YCrCb data

can be input in 4:2:2. In 4:2:2 input mode, the Y data is input

on Pins Y7–Y0 and the CrCb data on Pins C7–C0.

If the YCrCb data does not conform to SMPTE 293M (525p),

ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE

296M (720p), or BTA T-1004/1362, the async timing mode

must be used.

ADV7330

MPEG2

DECODER

VSYNC_I/P

HSYNC_I/P

BLANK_I/P

CLKIN

C[7:0]

Y[7:0]

INTERLACED

PROGRESSIVE

YCrCb

CbCr

27MHz

Figure 17. Progressive Scan Input Mode

Progressive Scan at 27 MHz (Dual Edge) or 54 MHz

Address(01h): Input Mode 100 or 111, Respectively

YCrCb progressive scan data can be input at 27 MHz or 54 MHz.

The input data is interleaved onto a single 8-bit bus and is input

on Pins Y7–Y0. When a 27 MHz clock is supplied, the data is

clocked in on the rising and falling edge of the input clock and

CLOCK EDGE [Address 01h, Bit 1] must be set accordingly.

The following figures show the possible conditions.

Y7–Y0

3FF

Cb0

Cr0

CLKIN

Figure 18a. Cb Data on Rising Edge—Clock Edge

Address 01h Bit 1 Should be Set to 0

Y7–Y0

3FF

Cb0

Cr0

CLKIN

Figure 18b. Y Data on Rising Edge—Clock Edge

Address 01h Bit 1 Should be Set to 1

With a 54 MHz clock, the data is latched on every rising edge.

PIXEL INPUT

DATA

3FF

Cb0

Cr0

CLKIN

Figure 18c. Input Sequence in PS Bit Interleaved

Mode (EAV/SAV)

ADV7330

MPEG2

DECODER

VSYNC_I/P

HSYNC_I/P

BLANK_I/P

CLKIN

Y[7:0]

INTERLACED

PROGRESSIVE

YCrCb

27MHz OR 54MHz

Figure 19. 1

8-Bit PS at 27 MHz or 54 MHz

ADV7330 Datasheet(PDF) 27 Page - Analog Devices

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