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ADV7330 Datasheet(PDF) 23 Page - Analog Devices |
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ADV7330 Datasheet(HTML) 23 Page - Analog Devices |
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23 / 76 page  REV. B ADV7330 –23– SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset Values 4Ah SD Timing Register 0 SD Slave/Master Mode 0Slave Mode 08h 1 Master Mode SD Timing Mode 00 Mode 0 01 Mode 1 10 Mode 2 11 Mode 3 SD BLANK Input 0 Enabled 1Disabled SD Luma Delay 00 No Delay 01 2 Clk Cycles 10 4 Clk Cycles 11 6 Clk Cycles SD Min. Luma Value 0– 40 IRE 1– 7.5 IRE SD Timing Reset x 0 0 0 0 0 0 0 A low-high-low transition will reset the internal SD timing counters. 4Bh SD Timing Register 1 SD HSYNC Width 0 0 TA = 1 Clk Cycle 00h 01 TA = 4 Clk Cycles 10 TA = 16 Clk Cycles 11 TA = 128 Clk Cycles SD HSYNC to VSYNC Delay 0 0 TB = 0 Clk Cycle 01 TB = 4 Clk Cycles 10 TB = 8 Clk Cycles 11 TB = 18 Clk Cycles SD HSYNC to VSYNC Rising x 0 T C = TB Edge Delay (Mode 1 Only) x1 TC = TB + 32 µs VSYNC Width (Mode 2 Only) 00 1 Clk Cycle 01 4 Clk Cycles 10 16 Clk Cycles 11 128 Clk Cycles HSYNC to Pixel Data Adjust 0 0 0 Clk Cycles 01 1 Clk Cycle 10 2 Clk Cycles 11 3 Clk Cycles 4Ch SD FSC Register 0 xx xx xx xx Subcarrier Frequency Bit 7–0 16h 4Dh SD FSC Register 1 xx xx xx xx Subcarrier Frequency Bit 15–8 7Ch 4Eh SD F SC Register 2 xx xx xx xx Subcarrier Frequency Bit 23–16 F0h 4Fh SD FSC Register 3 xx xx xx xx Subcarrier Frequency Bit 31–24 21h 50h SD F SC Phase xx xx xx xx Subcarrier Phase Bit 9–2 00h 51h SD Closed Captioning Extended Data on Even Fields xx xx xx xx Extended Data Bit 7–0 00h 52h SD Closed Captioning Extended Data on Even Fields xx xx xx xx Extended Data Bit 15–8 00h 53h SD Closed Captioning Data on Odd Fields xx x xx x xx Data Bit 7–0 00h 54h SD Closed Captioning Data on Odd Fields xx xx xx xx Data Bit 15–8 00h 55h SD Pedestal Register 0 Pedestal on Odd Fields 17 16 15 14 13 12 11 10 Setting any of these bits to 1 00h 56h SD Pedestal Register 1 Pedestal on Odd Fields 25 24 23 22 21 20 19 18 will disable pedestal on the 00h 57h SD Pedestal Register 2 Pedestal on Even Fields 17 16 15 14 13 12 11 10 line number indicated by the 00h 58h SD Pedestal Register 3 Pedestal on Even Fields 25 24 23 22 21 20 19 18 bit settings. 00h LINE 313 LINE 314 LINE 1 tB HSYNC VSYNC tA tC Figure 15. Timing Register 1 in PAL Mode |
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