ADV7330 datasheet(33/76 Pages) AD

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REV. B

ADV7330

–33–

Vertical Blanking Interval

The ADV7330 accepts input data that contains VBI data (such

as CGMS, WSS, VITS) in SD and HD modes.

For SMPTE 293M (525p) standards, VBI data can be inserted

on Lines 13 to 42 of each frame, or Lines 6 to 43 for the

ITU-R BT.1358 [625p] standard.

For SD NTSC, this data can be present on Lines 10 to 20; in PAL,

on Lines 7 to 22.

If VBI is disabled [Address 11h, Bit 4 for HD; Address 43h,

Bit4 for SD], VBI data is not present at the output and the entire

VBI is blanked. These control bits are valid in all master and

slave modes.

In Slave Mode 0, if VBI is enabled, the blanking bit in the

EAV/SAV code is overwritten; it is possible to use VBI in this

timing mode as well.

In Slave Mode 1 or 2, the BLANK control bit must be set to

enabled [Address 4Ah, Bit 3] to allow VBI data to pass through

the ADV7330; otherwise, the ADV7330 automatically blanks

the VBI to standard.

If CGMS is enabled and VBI disabled, the CGMS data will

nevertheless be available at the output.

Y C

EAV CODE

SAV CODE

ANCILLARY DATA

(HANC)

4 CLOCK

272 CLOCK

1280 CLOCK

4 CLOCK

344 CLOCK

1536 CLOCK

END OF ACTIVE

VIDEO LINE

START OF ACTIVE

VIDEO LINE

ANALOG

VIDEO

INPUT PIXELS

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

Figure 25. EAV/SAV Embedded Timing

FIELD

PIXEL

DATA

PAL = 44 CLOCK CYCLES

NTSC = 44 CLOCK CYCLES

PAL = 136 CLOCK CYCLES

NTSC = 208 CLOCK CYCLES

HSYNC

BLANK

Figure 26. Active Pixel Timing

SD Subcarrier Frequency Registers

[Subaddress 4Ch–4Fh]

Four 8-bit wide registers are used to set up the subcarrier

frequency. The value of these registers is calculated using the

following equation:

Subcarrier Frequency Register

Subcarrier FrequencyValue in one video line

MHz clk cycles in one video line

=×

#27

For example, NTSC mode,

Subcarrier FrequencyValue









×=

227 5

1716

569408542

Subcarrier Register Value = 21F07C1Eh

SD FSC Register 0: 1Eh

SD FSC Register 1: 7Ch

SD FSC Register 2: F0h

SD FSC Register 3: 21h

Refer to the MPU Port Description section for details on how to

access the subcarrier frequency registers.

Square Pixel Timing

[Register 42h, Bit 4]

In square pixel mode, the timing diagrams in Figures 25 and

26 apply.

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