ADV7330 datasheet(30/76 Pages) AD

30 / 76 page

REV. B

–30–

ADV7330

Table IV. Async Timing Mode Truth Table

Reference in

HSYNC_I/P

VSYNC_I/P

BLANK_I/P*

Figures 20a and 20b

→ 0

0 or 1

50% point of falling edge of tri-level horizontal sync signal

→ 1

0 or 1

25% point of rising edge of tri-level horizontal sync signal

→ 1

0 or 1

50% point of falling edge of tri-level horizontal sync signal

10 or 1

→ 1

50% start of active video

10 or 1

→ 0

50% end of active video

*When async timing mode is enabled, BLANK_I/P (Pin 25) becomes an active high input.

BLANK_I/P is set to active low at Address 10h, Bit 6.

HD Timing Reset

[Address 14h, Bit 0]

A timing reset is achieved in setting the HD timing reset control

bit at Address 14h from 0 to 1. In this state, the horizontal and

vertical counters will remain reset. When this bit is set back to

0, the internal counters will commence counting again. PLL must

be powered off by this mode.

The minimum time the pin has to be held high is one clock cycle,

otherwise this reset signal might not be recognized. This timing

reset applies to the HD timing counters only.

ADV7330 Datasheet(PDF) 30 Page - Analog Devices