DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
18
Final
Version: DM9601-DS-F01
June 22, 2002
10. Vendor Control and Status Register Set
The DM9601 implements several control and status
registers, which can be accessed by the USB vendor
register type commands. All CRs are set to their default
values by hardware or software reset unless they are
specified.
Register
Description
Offset
Default value
after reset
NCR
Network Control Register
00H
00H
NSR
Network Status Register
01H
00H
TCR
TX Control Register
02H
00H
TSR I
TX Status Register I
03H
00H
TSR II
TX Status Register II
04H
00H
RCR
RX Control Register
05H
00H
RSR
RX Status Register
06H
00H
ROCR
Receive Overflow Counter Register
07H
00H
BPTR
Back Pressure Threshold Register
08H
37H
FCTR
Flow Control Threshold Register
09H
38H
FCR
RX Flow Control Register
0AH
00H
EPCR
EEPROM & PHY Control Register
0BH
00H
EPAR
EEPROM & PHY Address Register
0CH
40H
EPDRL
EEPROM & PHY Low Byte Data Register
0DH
Unknown
EPDRH
EEPROM & PHY High Byte Data Register
0EH
Unknown
WCR
Wake Up Control Register
0FH
00H
PAR
Physical Address Register
10H-15H
Determined by
EEPROM
MAR
Multicast Address Register
16H-1DH
Unknown
GPCR
General Purpose Control Register
1EH
01H
GPR
General Purpose Register
1FH
Unknown
TWPAL
TX SRAM write pointer address low byte
20H
00H
TWPAH
TX SRAM write pointer address high byte
21H
00H
TRPAL
TX SRAM read pointer address low byte
22H
00H
TRPAH
TX SRAM read pointer address high byte
23H
00H
RWPAL
RX SRAM write pointer address low byte
24H
04H
RWPAH
RX SRAM write pointer address high byte
25H
0CH
RRPAL
RX SRAM read pointer address low byte
26H
00H
RRPAH
RX SRAM read pointer address high byte
27H
0CH
VID
Vendor ID
28H-29H
0A46H
PID
Product ID
2AH-2BH
9601H
CHIPR
CHIP revision
2CH
00H
USBDA
USB device address register
F0H
00H
RXC
Received packet counter register
F1H
00H
TXC/USBS
Transmit packet counter/USB status register
F2H
10H
USBC
USB control register
F4H
00H
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