DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Final
23
Version: DM9601-DS-F01
June 22, 2002
10.11 RX/TX Flow Control Register ( 0AH )
Bit
Name
Default
Description
7
TXP0
0,RW
TX pause packet, Auto clears after pause packet transmission completion.
Set to TX pause packet with time = 0000H
6
TXPF
0,RW
TX pause packet, Auto clears after pause packet transmission completion.
Set to TX pause packet with time = FFFFH.
5
TXPEN
0,RW
Force TX Pause Packet Enable
Enable the pause packet for high/low water threshold control.
4
BKPA
0,RW
Back pressure mode. This mode is for half duplex mode only. Generates a jam
pattern when any packet coming and RX SRAM over BPHW.
3
BKPM
0,RW
Back pressure mode. This mode is for half duplex mode only. Generates a jam
pattern when a packet’s DA match and RX SRAM over BPHW.
2
RXPS
0,R/C
RX pause packet status, latch and read clear
1
RXPCS
0,RO
RX pause packet current status
0
FLCE
0,RW
Flow Control Enable
Set to enable the flow control mode(i.e. to disable TX function).
10.12 EEPROM & PHY Control Register ( 0BH )
Bit
Name
Default
Description
7:6
RESERVED
0,RO
Reserved
5
REEP
0,RW
Reload EEPROM. Driver needs to clear it after operation complete.
4
WEP
0,RW
Write EEPROM enable
3
EPOS
0,RW
EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY.
2
ERPRR
0,RW
EEPROM Read or PHY Register Read Command. Driver needs to clear it after
operation complete.
1
ERPRW
0,RW
EEPROM Write or PHY Register Write Command. Driver needs to clear it after
operation complete.
0
ERRE
0,RO
EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress.
10.13 EEPROM & PHY Address Register ( 0CH )
Bit
Name
Default
Description
7:6
PHY_ADR
1,RW
PHY Address bit 1 and 0, the PHY address bit [4:2] is force to 0. Force to 01 if
internal PHY is selected
5:0
EROA
0,RW
EEPROM Word Address or PHY Register Address
10.14 EEPROM & PHY Data Register ( EE_PHY_L：
：
：
：
0DH
EE_PHY_H：
：
：
：
0EH )
Bit
Name
Default
Description
7:0
EE_PHY_L
X,RW
EEPROM or PHY Low Byte Data
7:0
EE_PHY_H
X,RW
EEPROM or PHY High Byte Data
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