DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Final
19
Version: DM9601-DS-F01
June 22, 2002
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where：
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
10.1 Network Control Register (00H)
Bit
Name
Default
Description
7
EXT_PHY
0,RW
Select External PHY When Set
When clear select Internal PHY. This bit will not be affected after a software reset
6
WAKEEN
0,RW
Wakeup Event Enable
When set, it enables the wakeup function. Clearing this bit will also clear all wakeup
event status.
This bit will not be affected after a software reset.
5
RESERVED
0,RO
Reserved
4
FCOL
0,RW
Force Collision Mode, used for testing.
3
FDX
0,RW
Full-Duplex Mode. Read only on Internal PHY mode. R/W on External PHY mode
2:1
LBK
00,RW
Loopback Mode
Bit 2 1
0
0
normal
0
1
MAC internal loopback
1
0
internal PHY digital loopback
1
1
internal PHY analog loopback
0
RST
0,RW
Software reset and auto clear after 10us
10.2 Network Status Register (01H)
Bit
Name
Default
Description
7
SPEED
X,RO
Media speed 0:100Mbps 1:10Mbps, when internal PHY is used. This bit is no
meaning when LINKST=0
6
LINKST
X,RO
Link status 0:link failed 1:link OK, when internal PHY is used
5
WAKEST
0,RW/C1
Wakeup Event Status
Clears by read or write 1. This bit will not be affected after a software reset
4
TXFULL
0,RO
TX FIFO Full
When there are two packets in TX SRAM, TX FIFO FULL will be set
3
TX2END
0,RW/C1
TX Packet 2 Complete Status
Clears by read or write 1.Transmit completion of packet index 2
2
TX1END
0,RW/C1
TX Packet 1 Complete Status
Clears by read or write 1. Transmit completion of packet index 1
1
RXOV
0,RO
RX FIFO Overflow
0
RXRDY
0,RO
RX Packet Ready, there are one or more packets in RX FIFO
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