DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
22
Final
Version: DM9601-DS-F01
June 22, 2002
1
CE
0,RO
CRC Error
It is set to indicate that the received frame ends with a CRC error.
0
FOE
0,RO
FIFO Overflow Error
It is set to indicate that a FIFO Overflow error happens during the frame reception.
10.8 Receive Overflow Counter Register ( 07H )
Bit
Name
Default
Description
7
RXFU
0,R/C
Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition.
6:0
ROC
0,R/C
Receive Overflow Counter
This is a statistic counter, which indicates that the received packet count upon FIFO
overflow
10.9 Back Pressure Threshold Register (08H)
Bit
Name
Default
Description
7:4
BPHW
3h, RW
Back Pressure High Water Overflow Threshold
MAC will generate the jam pattern when RX SRAM free space is lower than this
threshold value
Default is 3K-byte free space. Please don’t exceed SRAM size (1 unit=1K bytes)
3:0
JPT
7h, RW
Jam Pattern Time Default is 200us
bit3 bit2 bit1 bit0
time
0 0 0 0
5us
0 0 0 1
10us
0 0 1 0
15us
0 0 1 1
25us
0 1 0 0
50us
0 1 0 1
100us
0 1 1 0
150us
0 1 1 1
200us
1 0 0 0
250us
1 0 0 1
300us
1 0 1 0
350us
1 0 1 1
400us
1 1 0 0
450us
1 1 0 1
500us
1 1 1 0
550us
1 1 1 1
600us
10.10 Flow Control Threshold Register ( 09H )
Bit
Name
Default
Description
7:4
HWOT
3h, RW
RX FIFO High Water Overflow Threshold
Send a pause packet with pause_time=FFFFH when the RX RAM free space is
less than this value., If this value is zero, its meaning is no free RX SARM space.
Default is 3K-byte free space. Please don’t exceed SRAM size.
(1 unit=1K bytes)
3:0
LWOT
8h, RW
RX FIFO Low Water Overflow Threshold
Send a pause packet with pause_time=0000 when RX SARM free space is larger
than this value. This pause packet is enabled after high water pause packet is
transmitted. Default SRAM free space is 8K-byte. Please don’t exceed SRAM size.
(1 unit=1K bytes)
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