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DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
28
Final
Version: DM9601-DS-F01
June 22, 2002
11. MII Register Description
ADD
Name
15
14
13121110
9
8
7
6
5
4
3
2
1
0
00
CONTROL
Reset
Loop
back
Speed
select
Auto-N
Enable
Power
Down
Isolate Restart
Auto-N
Full
Duplex
Coll.
Test
Reserved
01
STATUS
T4
Cap.
TX FDX
Cap.
TXHDX
Cap.
10 FDX
Cap.
10 HDX
Cap.
Reserved
Pream.
Supr.
Auto-N
Compl.
Remote
Fault
Auto-N
Cap.
Link
Status
Jabber
Detect
Extd
Cap.
02
PHYID1
0
0
0000
01
10
0
0
0
0
00
03
PHYID2
1
0
1110
Model No.
Version No.
04
Auto-Neg.
Advertise
Next
Page
FLP Rcv
Ack
Remote
Fault
Reserved
FC
Adv
T4
Adv
TX FDX
Adv
TXHDX
Adv
10 FDX
Adv
10 HDX
Adv
Advertised Protocol Selector Field
05
Link Part.
Ability
LP Next
Page
LP
Ack
LP
RF
Reserved
LP
FC
LP
T4
LP
TX FDX
LP
TXHDX
LP
10 FDX
LP
10 HDX
Link Partner Protocol Selector Field
06
Auto-Neg.
Expansion
Reserved
Pardet
Fault
LP Next
Pg Able
Next Pg
Able
New
Pg
Rcv
LP AutoN
Cap.
16
Specified
Config.
BP 4B5B
BP
SCR
BP
ALIGN
BP_AD
POK
Rsvd
TX
Rsvd
Rsvd
Force
100LNK
Re-served
RPDCTR
-EN
Reset
St. Mch
Pream.
Supr.
Sleep
mode
Remote
LoopOut
17
Specified
Conf/Stat
100 FDX
100
HDX
10
FDX
10
HDX
Reserved
PHY ADDR [4:0]
Auto-N. Monitor Bit [3:0]
18
10T
Conf/Stat
Rsvd
LP
Enable
HBE
Enable
SQUE
Enable
JAB
Enable
10T
Serial
Reserved
Polarity
Reverse
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where：
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
(PIN#)
Value latched in from pin # at reset
<Access Type>:
RO = Read Only
RW = Read/Write
<Attribute (s)>:
SC = Self Clearing
P = Value Permanently Set
LL = Latching Low
LH = Latching High
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